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1. WO2021041003 - ARCHITECTURE-BASED POWER MANAGEMENT FOR A MEMORY DEVICE

Publication Number WO/2021/041003
Publication Date 04.03.2021
International Application No. PCT/US2020/045412
International Filing Date 07.08.2020
IPC
G11C 5/14 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by group G11C11/63
14Power supply arrangements
G11C 8/12 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
12Group selection circuits, e.g. for memory block selection, chip selection, array selection
G06F 3/06 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from, or digital output to, record carriers
G11C 5/04 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by group G11C11/63
02Disposition of storage elements, e.g. in the form of a matrix array
04Supports for storage elements; Mounting or fixing of storage elements on such supports
CPC
G06F 1/3225
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of power-saving mode
3206Monitoring of events, devices or parameters that trigger a change in power modality
3215Monitoring of peripheral devices
3225of memory devices
G06F 1/3275
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of power-saving mode
3234Power saving characterised by the action undertaken
325Power saving in peripheral device
3275Power saving in memory, e.g. RAM, cache
G06F 1/3287
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of power-saving mode
3234Power saving characterised by the action undertaken
3287by switching off individual functional units in the computer system
G06F 12/00
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
G06F 9/4401
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
44Arrangements for executing specific programs
4401Bootstrapping
G11C 11/2297
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
22using ferroelectric elements
225Auxiliary circuits
2297Power supply circuits
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • LAURENT, Christophe, Vincent Antoine
  • MARTINELLI, Andrea
  • MIRICHIGNI, Graziano
Agents
  • HARRIS, Philip
Priority Data
16/551,59726.08.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) ARCHITECTURE-BASED POWER MANAGEMENT FOR A MEMORY DEVICE
(FR) GESTION DE PUISSANCE BASÉE SUR L'ARCHITECTURE POUR DISPOSITIF DE MÉMOIRE
Abstract
(EN)
Methods, systems, and devices for architecture-based power management for a memory device are described. Aspects include operating a first memory bank within a memory device in a first mode and a second memory bank within the memory device in a second mode. The memory device may receive a power down command for the first memory bank while operating the first memory bank in the first mode and the second memory bank in the second mode and switch the first memory bank from the first mode to a first low power mode while maintaining the second memory bank in the second mode. The first low power mode corresponds to less power consumption by the first memory bank than the first mode. In some cases, switching the first memory bank from the first mode to the first low power mode includes deactivating circuitry dedicated to the first memory bank.
(FR)
Des procédés, des systèmes, et des dispositifs destinés à la gestion de puissance basée sur l'architecture pour un dispositif de mémoire, sont décrits. Des aspects comprennent le fonctionnement d'une première banque de mémoire à l'intérieur d'un dispositif de mémoire dans un premier mode et d'une seconde banque de mémoire à l'intérieur du dispositif de mémoire dans un second mode. Le dispositif de mémoire peut recevoir une commande de mise hors tension pour la première banque de mémoire tout en faisant fonctionner la première banque de mémoire dans le premier mode et la seconde banque de mémoire dans le second mode et commuter la première banque de mémoire du premier mode à un premier mode de faible puissance tout en maintenant la seconde banque de mémoire dans le second mode. Le premier mode de faible puissance correspond à moins de consommation de puissance par la première banque de mémoire que le premier mode. Dans certains cas, la commutation de la première banque de mémoire du premier mode au premier mode de faible puissance comprend la désactivation de circuits dédiés à la première banque de mémoire.
Also published as
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