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1. WO2021040196 - APPARATUS AND METHOD FOR OPERATING MULTIPLE FPGAS IN WIRELESS COMMUNICATION SYSTEM

Publication Number WO/2021/040196
Publication Date 04.03.2021
International Application No. PCT/KR2020/007109
International Filing Date 02.06.2020
IPC
G06F 13/16 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
G06F 7/76 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
76Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
G06F 12/02 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
CPC
G06F 12/02
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
G06F 12/023
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
0223User address space allocation, e.g. contiguous or non contiguous base addressing
023Free address space management
G06F 13/16
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
G06F 13/1652
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
1605based on arbitration
1652in a multiprocessor architecture
G06F 2212/154
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
15Use in a specific computing environment
154Networked environment
G06F 7/76
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
76Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
Applicants
  • 삼성전자 주식회사 SAMSUNG ELECTRONICS CO., LTD. [KR]/[KR]
Inventors
  • 배진우 BAE, Jinwoo
  • 최현주 CHOI, Hyunjoo
Agents
  • 권혁록 KWON, Hyuk-Rok
  • 이정순 LEE, Jeong-Soon
Priority Data
10-2019-010541427.08.2019KR
Publication Language Korean (KO)
Filing Language Korean (KO)
Designated States
Title
(EN) APPARATUS AND METHOD FOR OPERATING MULTIPLE FPGAS IN WIRELESS COMMUNICATION SYSTEM
(FR) APPAREIL ET PROCÉDÉ POUR FAIRE FONCTIONNER PLUSIEURS FPGA DANS UN SYSTÈME DE COMMUNICATION SANS FIL
(KO) 무선 통신 시스템에서 다중 FPGA를 운영하기 위한 장치 및 방법
Abstract
(EN)
The present disclosure relates to a 5th generation (5G) or pre-5G communication system for supporting a higher data rate than a 4th generation (4G) communication system such as long term evolution (LTE). According to various embodiments of the present disclosure, provided is an apparatus of a base station in a wireless communication system, the apparatus comprising: a master field programmable gate array (FPGA); a plurality of slave FPGAs controlled by the master FPGA; and an address masker connected to the master FPGA and the plurality of slave FPGAs, wherein the address masker is configured to: receive different address bits that are assigned to each of the plurality of slave FPGAs by the master FPGA; for the different address bits, mask bit values at a specific position with the same value; and transmit masked address bits corresponding to each of the plurality of slave FPGAs.
(FR)
La présente invention concerne un système de communication de 5ème génération (5G) ou pré-5G destiné à prendre en charge un débit de données supérieur à celui d'un système de communication de 4ème génération (4G), tel que la technologie d'évolution à long terme (LTE). Selon divers modes de réalisation, la présente invention concerne un appareil d'une station de base dans un système de communication sans fil, l'appareil comprenant : un réseau de portes programmables in situ (FPGA) maître ; une pluralité de FPGA esclaves commandés par le FPGA maître ; et une unité de masquage d'adresses connectée au FPGA maître et à la pluralité de FPGA esclaves, l'unité de masquage d'adresses étant configurée pour : recevoir différents bits d'adresses qui sont attribués à chacun de la pluralité de FPGA esclaves par le FPGA maître ; pour les différents bits d'adresses, masquer des valeurs de bits à une position spécifique avec la même valeur ; et transmettre des bits d'adresses masqués correspondant à chacun de la pluralité de FPGA esclaves.
(KO)
본 개시는 LTE(Long Term Evolution)와 같은 4G(4th generation) 통신 시스템 이후 보다 높은 데이터 전송률을 지원하기 위한 5G(5th generation) 또는 pre-5G 통신 시스템에 관련된 것이다. 본 개시의 다양한 실시 예들에 따르면, 무선 통신 시스템에서 기지국의 장치에 있어서, 마스터 FPGA(field programmable gate array); 마스터 FPGA의 제어를 받는 복수의 슬레이브 FPGA들; 및 마스터 FPGA 및 복수의 슬레이브 FPGA들과 연결된 어드레스 마스커를 포함하며, 어드레스 마스커는, 마스터 FPGA에 의하여 각각의 복수의 슬레이브 FPGA들에게 할당된 서로 다른 어드레스 비트들을 수신하고, 서로 다른 어드레스 비트들에 대하여 특정 위치의 비트 값들을 동일한 값으로 마스킹하며, 각각의 복수의 슬레이브 FPGA들에게 대응하는 마스킹된 어드레스 비트들을 송신하도록 구성된 장치가 제공된다.
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