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1. WO2021040178 - PACKAGING SUBSTRATE AND SEMICONDUCTOR DEVICE COMPRISING SAME

Publication Number WO/2021/040178
Publication Date 04.03.2021
International Application No. PCT/KR2020/004898
International Filing Date 10.04.2020
IPC
H01L 23/48 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/498 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488consisting of soldered or bonded constructions
498Leads on insulating substrates
H01L 23/522 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
CPC
H01L 2224/14181
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
14of a plurality of bump connectors
141Disposition
1418being disposed on at least two different sides of the body, e.g. dual array
14181On opposite sides of the body
H01L 23/48
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
H01L 23/498
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
488consisting of soldered ; or bonded; constructions
498Leads, ; i.e. metallisations or lead-frames; on insulating substrates, ; e.g. chip carriers
H01L 23/522
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Applicants
  • 에스케이씨 주식회사 SKC CO., LTD. [KR]/[KR]
Inventors
  • 노영호 RHO, Youngho
  • 김성진 KIM, Sungjin
  • 김진철 KIM, Jincheol
Agents
  • 정화승 CHUNG, Hwaseung
Priority Data
62/890,68923.08.2019US
Publication Language Korean (KO)
Filing Language Korean (KO)
Designated States
Title
(EN) PACKAGING SUBSTRATE AND SEMICONDUCTOR DEVICE COMPRISING SAME
(FR) SUBSTRAT DE BOÎTIER ET DISPOSITIF À SEMI-CONDUCTEUR LE COMPRENANT
(KO) 패키징 기판 및 이를 포함하는 반도체 장치
Abstract
(EN)
An embodiment relates to a packaging substrate and a semiconductor device, and comprises: an element unit including semiconductor elements; and a packaging substrate electrically connected to the element unit, wherein a glass substrate is applied to the packaging substrate as a core so as to more closely connect the semiconductor elements and a motherboard, such that an electrical signal is transmitted at as short a distance as possible. Accordingly, provided is a packaging substrate which can greatly improve electrical properties, such as signal transmission speed, etc., can further simplify an insulation film treatment process by substantially preventing the occurrence of parasitic elements, and is applicable to a high-speed circuit.
(FR)
Un mode de réalisation de la présente invention concerne un substrat de boîtier et un dispositif à semi-conducteur, une unité d'élément comprenant des éléments semi-conducteur ; et un substrat de boîtier connecté électriquement à l'unité d'élément, un substrat de verre étant appliqué au substrat de boîtier en tant que noyau de manière à obtenir une connexion plus proche entre l'élément semi-conducteur et une carte mère, permettant ainsi à un signal électrique d'être transmis sur une distance aussi courte que possible. En conséquence, l'invention concerne un substrat de boîtier qui peut grandement améliorer les propriétés électriques, telle qu'une vitesse de transmission de signal, etc, peut en outre simplifier un processus de traitement de film d'isolation en empêchant sensiblement l'apparition d'éléments parasites, et est applicable à un circuit à grande vitesse.
(KO)
구현예는 패키징 기판 및 반도체 장치에 관한 것으로, 반도체 소자를 포함하는 소자부;와 상기 소자부와 전기적으로 연결되는 패키징 기판;을 포함하며 상기 패키징 기판에 유리기판을 코어로 적용하여 반도체 소자와 마더보드 사이를 보다 가깝게 연결해 전기적 신호가 최대한 짧은 거리로 전달되도록 한다. 이에, 신호 전달 속도 등의 전기적 특성을 크게 향상시키고, 기생소자 발생을 실질적으로 막아 절연막 처리 공정을 보다 단순화시킬 수 있으며, 고속 회로에 적용 가능한 패키징 기판을 제공한다.
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