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1. WO2021039268 - SEMICONDUCTOR DEVICE

Publication Number WO/2021/039268
Publication Date 04.03.2021
International Application No. PCT/JP2020/029286
International Filing Date 30.07.2020
IPC
H01L 29/786 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
786Thin-film transistors
H01L 21/336 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334Multistep processes for the manufacture of devices of the unipolar type
335Field-effect transistors
336with an insulated gate
CPC
H01L 29/786
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
78with field effect produced by an insulated gate
786Thin film transistors, ; i.e. transistors with a channel being at least partly a thin film
Applicants
  • 株式会社ジャパンディスプレイ JAPAN DISPLAY INC. [JP]/[JP]
Inventors
  • 花田 明紘 HANADA Akihiro
  • 海東 拓生 KAITOH Takuo
  • 津吹 将志 TSUBUKU Masashi
Agents
  • ポレール特許業務法人 POLAIRE I.P.C.
Priority Data
2019-15809630.08.2019JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置
Abstract
(EN)
The present invention addresses the problem of suppressing the threshold voltage variation ΔVth for a thin-film transistor (TFT) made of an oxide semiconductor. An exemplary means of the present invention for solving such a problem is as follows. This semiconductor device has a TFT made of an oxide semiconductor. The semiconductor device is characterized in that: the oxide semiconductor includes a channel region 104, a source region 1042, a drain region 1043, and a lightly doped drain (LDD) region 1041 disposed between the channel region and the source region, and between the channel region and the drain region; the resistivity of the LDD region 1041 is less than the resistivity of the channel region and greater than the resistivity of the source region or of the drain region; a source electrode 108 is formed to overlap with the source region 1042; a drain electrode 109 is formed to overlap with the drain region 1043; and the thickness of the LDD region 1041 of the oxide semiconductor is greater than the thickness of the channel region 104.
(FR)
La présente invention aborde le problème de suppression de la variation de tension de seuil ΔVth pour un transistor à couches minces (TFT) constitué d'un semi-conducteur à oxyde. Un moyen exemplaire de la présente invention pour résoudre le problème susmentionné est comme suit. Ce dispositif à semi-conducteur comprend un transistor à couches minces (TFT) constitué d'un semi-conducteur à oxyde. Le dispositif à semi-conducteur est caractérisé en ce que : le semi-conducteur à oxyde comprend une région de canal 104, une région de source 1042, une région de drain 1043, et une région de drain 1041 légèrement dopée (LDD) disposée entre la région de canal et de la région de source, et entre la région de canal et la région de drain ; la résistivité de la région LDD 1041 est inférieure à la résistivité de la région de canal et supérieure à la résistivité de la région de source ou de la région de drain ; une électrode de source 108 est formée pour se chevaucher avec la région de source 1042 ; une électrode de drain 109 est formée pour se chevaucher avec la région de drain 1043 ; et l'épaisseur de la région LDD 1041 du semi-conducteur à oxyde est supérieure à l'épaisseur de la région de canal 104.
(JA)
本発明の課題は、酸化物半導体による薄膜トランジスタ(TFT)において、閾値電圧の変動ΔVthを抑える。このような課題を解決するための、本発明の代表的手段はつぎのとおりである。酸化物半導体によるTFTを有する半導体装置であって、前記酸化物半導体は、チャネル領域104、ソース領域1042、ドレイン領域1043と、前記チャネル領域と前記ソース領域及び前記ドレイン領域の間にLDD(Lightly Doped Drain)領域1041を有し、前記LDD領域1041の抵抗率は、前記チャネル領域の抵抗率よりも小さく、前記ソース領域あるいは前記ドレイン領域の抵抗率よりも大きく、ソース電極108は前記ソース領域1042と重複して形成され、ドレイン電極109は前記ドレイン領域1043と重複して形成され、前記酸化物半導体の前記LDD領域1041の厚さは、前記チャネル領域104の厚さよりも大きいことを特徴とする半導体装置。
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