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1. WO2021035800 - HIGH-PERFORMANCE INSTRUCTION SEQUENCE CONTROL MODULE BASED ON SYNCHRONOUS CHANNEL OPERATION ARCHITECTURE FLASH MASTER CONTROL

Publication Number WO/2021/035800
Publication Date 04.03.2021
International Application No. PCT/CN2019/105067
International Filing Date 10.09.2019
IPC
G06F 3/06 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from, or digital output to, record carriers
CPC
G06F 3/061
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers ; , e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0602specifically adapted to achieve a particular effect
061Improving I/O performance
G06F 3/0658
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers ; , e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0628making use of a particular technique
0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
0658Controller construction arrangements
G06F 3/0659
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers ; , e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0628making use of a particular technique
0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
0659Command handling arrangements, e.g. command buffers, queues, command scheduling
G06F 3/0679
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers ; , e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0668adopting a particular infrastructure
0671In-line storage system
0673Single storage device
0679Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
Applicants
  • 江苏华存电子科技有限公司 JIANGSU HUACUN ELECTRONIC TECHNOLOGY CO., LTD. [CN]/[CN]
Inventors
  • 陈育鸣 CHEN, Yuming
  • 李庭育 LI, Tingyu
  • 魏智汎 WEI, Zhifan
  • 洪振洲 HONG, Zhenzhou
Priority Data
201910794138.627.08.2019CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) HIGH-PERFORMANCE INSTRUCTION SEQUENCE CONTROL MODULE BASED ON SYNCHRONOUS CHANNEL OPERATION ARCHITECTURE FLASH MASTER CONTROL
(FR) MODULE DE COMMANDE DE SÉQUENCE D'INSTRUCTIONS HAUTE PERFORMANCE BASÉ SUR UNE COMMANDE MAÎTRE FLASH À ARCHITECTURE DE FONCTIONNEMENT DE CANAL SYNCHRONE
(ZH) 基于同步通道运作架构闪存主控之高效能指令序列控制模块
Abstract
(EN)
A high-performance instruction sequence controller based on synchronous channel operation architecture flash master control, comprising a master control chip (1), a central controller (2), flash storage controllers (3), flash storage components (4), a central control register (5), a flash super page/block sequence manager (6), and a parameter sequence table (7). The central controller (2) and a plurality of flash storage controllers (3) are provided in the master control chip (1). The central controller (2) is connected to all the flash storage controllers (3). Each flash storage controller (3) corresponds to a flash storage component (4). The central control register (5), the flash super page/block sequence manager (6), and the parameter sequence table (7) are provided in the central controller (2). By means of this solution, all flash interfaces can issue instruction sequences simultaneously, thereby effectively improving the working efficiency of the whole flash master control module.
(FR)
L'invention concerne un contrôleur de séquence d'instructions haute performance basé sur une commande maître flash à architecture de fonctionnement de canal synchrone, comprenant une puce de commande maître (1), un contrôleur central (2), des contrôleurs de stockage flash (3), des composants de stockage flash (4), un registre central de commande (5), un gestionnaire de séquence de super page/bloc flash (6) et une table de séquence de paramètres (7). Le contrôleur central (2) et une pluralité de dispositifs de commande de stockage flash (3) sont disposés dans la puce de commande maître (1). Le contrôleur central (2) est connecté à tous les contrôleurs de stockage flash (3). Chaque contrôleur de stockage flash (3) correspond à un composant de stockage de flash (4). Le registre central de commande (5), le gestionnaire de séquence de super page/bloc flash (6) et la table de séquence de paramètres (7) sont disposés dans le contrôleur central (2). Au moyen de cette solution, toutes les interfaces flash peuvent émettre simultanément des séquences d'instructions, ce qui permet d'améliorer efficacement l'efficacité de travail de l'ensemble du module de commande maître de flash.
(ZH)
一种基于同步通道运作架构闪存主控之高效能指令序列控制器,包括主控芯片(1)、中枢控制器(2)、闪存储存控制器(3)、闪存储存组件(4)、中枢控制寄存器(5)、闪存超级页/块序列管理器(6)、参数序列表(7),主控芯片(1)内部设置有中枢控制器(2)和若干个闪存储存控制器(3),中枢控制器(2)与所有的闪存储存控制器(3)相连,每个闪存储存控制器(3)与闪存储存组件(4)相对应,中枢控制器(2)内部设置有中枢控制寄存器(5)、闪存超级页/块序列管理器(6)及参数序列表(7)。该方案各个闪存接口可以同时发出指令序列,有效的提升整体闪存主控模块的工作效能。
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