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1. WO2021011189 - FACILITATING SEQUENTIAL DATA TRANSFORMATIONS VIA DIRECT MEMORY ACCESS

Publication Number WO/2021/011189
Publication Date 21.01.2021
International Application No. PCT/US2020/040307
International Filing Date 30.06.2020
IPC
G06F 13/28 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
20for access to input/output bus
28using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/12 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
10Program control for peripheral devices
12using hardware independent of the central processor, e.g. channel or peripheral processor
G06F 13/16 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
G06F 9/30 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
CPC
G06F 13/28
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
20for access to input/output bus
28using burst mode transfer, e.g. direct memory access ; DMA; , cycle steal
G06F 9/3001
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30007to perform operations on data operands
3001Arithmetic instructions
G06F 9/30112
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30098Register arrangements
30105Register structure
30112for variable length data, e.g. single or double registers
Applicants
  • KILSDONK, Daniel [US]/[US]
Inventors
  • KILSDONK, Daniel
Agents
  • SOLOMON, Mark, B.
  • BROOK, David, E.
  • SMITH, James, M.
  • CARROLL, Alice, O.
  • SOLOMON, Mark, B.
Priority Data
62/874,39315.07.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) FACILITATING SEQUENTIAL DATA TRANSFORMATIONS VIA DIRECT MEMORY ACCESS
(FR) FACILITATION DE TRANSFORMATIONS DE DONNÉES SÉQUENTIELLES PAR L'INTERMÉDIAIRE D'UN ACCÈS DIRECT À LA MÉMOIRE
Abstract
(EN)
A direct memory access (DMA) device provides for transforming source data as it is transferred to a destination memory space. The transformation can encompass a range of arithmetic logic unit (ALU) operations. The transformation can include discerning comparative matches in the source address space, such that matched-indice-reference-offsets are transferred to destination memory. A processor requesting the transfer can also configure the transformation to be completed by writing configuration data to memory and/or programming the DMA device. In transforming data as it is transferred, the DMA device can obviate time-consuming processing otherwise done after conventional DMA transfers.
(FR)
L'invention concerne un dispositif d'accès direct à la mémoire (DMA) permettant de transformer des données sources tandis qu'elles sont transférées vers un espace mémoire de destination. La transformation peut englober une plage d'opérations d'unité arithmétique logique (ALU). La transformation peut consister à discerner des correspondances comparatives dans l'espace d'adresse source, de telle sorte que des décalages de références d'indices appariés sont transférés vers la mémoire de destination. Un processeur demandant le transfert peut également configurer la transformation afin qu'elle soit achevée en écrivant des données de configuration dans la mémoire et/ou en programmant le dispositif DMA. En transformant les données pendant leur transfert, le dispositif DMA peut éviter un traitement chronophage qui est autrement effectué après les transferts DMA classiques.
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