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1. WO2021002934 - METHOD OF FORMING SPLIT GATE MEMORY CELLS

Publication Number WO/2021/002934
Publication Date 07.01.2021
International Application No. PCT/US2020/031920
International Filing Date 07.05.2020
IPC
H01L 27/11536 2017.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
11526characterised by the peripheral circuit region
11531Simultaneous manufacturing of periphery and memory cells
11534including only one type of peripheral transistor
11536with a control gate layer also being used as part of the peripheral transistor
H01L 21/28 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
H01L 29/423 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40Electrodes
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
Applicants
  • SILICON STORAGE TECHNOLOGY, INC. [US]/[US]
Inventors
  • XING, Leo
  • WANG, Chunming
  • DO, Nhan
  • LIU, Guo Yong
  • DIAO, Melvin
  • LIU, Xian
Agents
  • LIMBACH, Alan
Priority Data
16/868,14306.05.2020US
201910588914.702.07.2019CN
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) METHOD OF FORMING SPLIT GATE MEMORY CELLS
(FR) PROCÉDÉ DE FORMATION DE CELLULES DE MÉMOIRE À GRILLE DIVISÉE
Abstract
(EN)
A method of forming a memory device includes forming a second insulation layer on a first conductive layer formed on a first insulation layer formed on semiconductor substrate. A trench is formed into the second insulation layer extending down and exposing a portion of the first conductive layer, which is etched or oxidized to have a concave upper surface. Two insulation spacers are formed along sidewalls of the trench, having inner surfaces facing each other and outer surfaces facing away from each other. A source region is formed in the substrate between the insulation spacers. The second insulation layer and portions of the first conductive layer are removed to form floating gates under the insulation spacers. A third insulation layer is formed on side surfaces of the floating gates. Two conductive spacers are formed along the outer surfaces. Drain regions are formed in the substrate adjacent the conductive spacers.
(FR)
L'invention concerne un procédé de formation d'un dispositif de mémoire qui consiste à former une deuxième couche d'isolation sur une première couche conductrice formée sur une première couche d'isolation formée sur un substrat semi-conducteur. Une tranchée est formée dans la seconde couche d'isolation s'étendant vers le bas et exposant une partie de la première couche conductrice, qui est gravée ou oxydée pour avoir une surface supérieure concave. Deux entretoises d'isolation sont formées le long de parois latérales de la tranchée, ayant des surfaces internes en regard l'une de l'autre et des surfaces externes opposées l'une à l'autre. Une région de source est formée dans le substrat entre les entretoises d'isolation. La deuxième couche d'isolation et des parties de la première couche conductrice sont retirées pour former des grilles flottantes sous les entretoises d'isolation. Une troisième couche d'isolation est formée sur les surfaces latérales des grilles flottantes. Deux entretoises conductrices sont formées le long des surfaces externes. Des régions de drain sont formées dans le substrat adjacent aux entretoises conductrices.
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