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1. WO2020240113 - METHOD FOR IMPLEMENTING A HARDWARE ACCELERATOR OF A NEURAL NETWORK

Publication Number WO/2020/240113
Publication Date 03.12.2020
International Application No. PCT/FR2020/050822
International Filing Date 18.05.2020
IPC
G06N 3/063 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
063using electronic means
G06N 3/04 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
04Architecture, e.g. interconnection topology
G06N 3/10 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
10Simulation on general purpose computers
G06N 3/08 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
08Learning methods
CPC
G06N 3/0454
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
04Architectures, e.g. interconnection topology
0454using a combination of multiple neural nets
G06N 3/063
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
063using electronic means
G06N 3/08
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
08Learning methods
G06N 3/105
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
10Simulation on general purpose computers
105Shells for specifying net layout
Applicants
  • BULL SAS [FR]/[FR]
Inventors
  • BOURGE, Alban
  • MOGNOL, Meven
  • SINITAMBIRIVOUTIN, Emrick
Agents
  • PLASSERAUD IP
Priority Data
190568128.05.2019FR
Publication Language French (FR)
Filing Language French (FR)
Designated States
Title
(EN) METHOD FOR IMPLEMENTING A HARDWARE ACCELERATOR OF A NEURAL NETWORK
(FR) PROCEDE D'IMPLEMENTATION D'UN ACCELERATEUR MATERIEL D'UN RESEAU DE NEURONES
Abstract
(EN)
The invention relates to a method for implementing a hardware accelerator of a neural network, comprising: a step of interpreting an algorithm of the neural network in binary format, converting the neural network algorithmin in binary format into a graphical representation, selecting base blocks from a library of predetermined base blocks, carrying out organisation of the selected base blocks, configuring internal parameters for the base blocks of the organisation in such a manner that the organisation of the selected and parameterised base blocks corresponds to the graphical representation, a step of determining an initial set of weights of the neural network, a step of completely synthesising the organisation of the selected and parameterised base blocks, on the one hand, in a preselected FPGA programmable logic circuit (41) in a hardware accelerator (42) of the neural network and, on the other hand, in a control software item for this hardware accelerator (42), this hardware accelerator (42) being specifically dedicated to the neural network so as to represent the whole of the architecture of the neural network without needing access to an external memory (44) for the FPGA programmable logic circuit (41) when passing from one layer to another layer of the neural network, a step of loading (48) the initial set of weights of the neural network in the hardware accelerator (42).
(FR)
L'invention concerne un procédé d'implémentation d'un accélérateur matériel d'un réseau de neurones, comprenant : une étape d'interprétation d'un algorithme du réseau de neurones en format binaire, convertissant l'algorithme de réseau de neurones en format binaire en une représentation sous forme de graphe, sélectionnant des blocs de base dans une bibliothèque de blocs de base prédéterminés, réalisant une organisation des blocs de base sélectionnés, configurant des paramètres internes des blocs de base de l'organisation, de sorte que l'organisation des blocs de base sélectionnés et paramétrés corresponde à ladite représentation sous forme de graphe, une étape de détermination d'un jeu initial de poids du réseau de neurones, une étape de synthétisation complète de l'organisation des blocs de base sélectionnés et paramétrés d'une part sur un circuit logique programmable FPGA (41) présélectionné en un accélérateur matériel (42) du réseau de neurones et d'autre part en un logiciel pilote de cet accélérateur matériel (42), cet accélérateur matériel (42) étant spécifiquement dédié au réseau de neurones de manière à être représentatif de l'ensemble de l'architecture du réseau neurones sans nécessiter d'accès à une mémoire externe (44) au circuit logique programmable FPGA (41) lors du passage d'une couche à une autre couche du réseau de neurones, une étape de chargement (48) du jeu initial de poids du réseau de neurones dans l'accélérateur matériel (42).
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Latest bibliographic data on file with the International Bureau