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1. WO2020230413 - INFORMATION PROCESSING DEVICE

Publication Number WO/2020/230413
Publication Date 19.11.2020
International Application No. PCT/JP2020/008704
International Filing Date 02.03.2020
IPC
G06F 12/00 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
G06F 13/38 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
CPC
G06F 13/1605
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
1605based on arbitration
G06F 13/1668
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
1668Details of memory controller
G06F 13/372
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
36for access to common bus or bus system
368with decentralised access control
372using a time-dependent priority, e.g. individually loaded time counters or time slot
G06F 13/4282
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
42Bus transfer protocol, e.g. handshake; Synchronisation
4282on a serial bus, e.g. I2C bus, SPI bus
Applicants
  • オムロン株式会社 OMRON CORPORATION [JP]/[JP]
Inventors
  • 玉井 俊規 TAMAI, Toshinori
Agents
  • 村上 尚 MURAKAMI, Takashi
Priority Data
2019-09318216.05.2019JP
Publication Language Japanese (ja)
Filing Language Japanese (JA)
Designated States
Title
(EN) INFORMATION PROCESSING DEVICE
(FR) DISPOSITIF DE TRAITEMENT D'INFORMATIONS
(JA) 情報処理装置
Abstract
(EN) The present invention suppresses the occurrence of memory contention without executing, in an operation unit of a control device, a reconciliation process for preventing memory contention. Provided is a unit (20) that causes transmission of smallest payload data (D8) to a communication interface (42) to be in standby during a time period (T3) from a time (t5), at which it is determined that a transmission time (T2) of smallest payload data (D6) exceeds a reference value during a control cycle (C2), to a time (t6) at which the communication interface (42) transmits the smallest payload data (D8) to be transmitted next after the most recent smallest payload data (D7) transmitted at the time (t5).
(FR) La présente invention supprime l'apparition de conflit de mémoire sans exécuter, dans une unité de fonctionnement d'un dispositif de commande, un processus de rapprochement pour empêcher un conflit de mémoire. L'invention concerne une unité (20) qui amène la transmission des données de charge utile les plus petites (D8) à une interface de communication (42) à se trouver en veille pendant une période de temps (T3) à partir d'un instant (t5), auquel il est déterminé qu'un moment de transmission (T2) des données de charge utile les plus petites (D6) dépasse une valeur de référence pendant un cycle de commande (C2), jusqu'à un instant (t6) auquel l'interface de communication (42) transmet les prochaines plus petites données de charge utile (D8) à transmettre après les plus petites données de charge utile transmises le plus récemment (D7) à l'instant (t5).
(JA) メモリ競合を防止するための調停処理を制御装置の演算部に実行させることなく、メモリ競合の発生を抑制する。制御周期(C2)において最小ペイロードデータ(D6)の送信時間(T2)が基準値を超えると判定された時刻(t5)から、時刻(t5)において送信済みの直近の最小ペイロードデータ(D7)の次に送信される最小ペイロードデータ(D8)を通信インタフェース(42)が送信する時刻(t6)までの期間(T3)において、通信インタフェース(42)に最小ペイロードデータ(D8)の送信を待機させるユニット(20)。
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