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1. WO2020226810 - TRISTATE AND PASS-GATE BASED CIRCUIT WITH FULL SCAN COVERAGE

Publication Number WO/2020/226810
Publication Date 12.11.2020
International Application No. PCT/US2020/026939
International Filing Date 06.04.2020
IPC
H03K 19/173 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02using specified components
173using elementary logic circuits as components
H03K 19/017 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
01Modifications for accelerating switching
017in field-effect transistor circuits
CPC
H03K 17/693
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
17Electronic switching or gating, i.e. not by contact-making and –breaking
51characterised by the components used
56by the use, as active elements, of semiconductor devices
687the devices being field-effect transistors
693Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
H03K 19/1737
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
173using elementary logic circuits as components
1733Controllable logic circuits
1737using multiplexers
H03K 2217/0054
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
2217Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
0054Gating switches, e.g. pass gates
Applicants
  • INTEL CORPORATION [US]/[US]
Inventors
  • RAGHURAMAN, Eashwar
  • SETHURAMAN, Satish
  • BRAZIL, Edward
Agents
  • MUGHAL, Usman A.
Priority Data
16/404,61606.05.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) TRISTATE AND PASS-GATE BASED CIRCUIT WITH FULL SCAN COVERAGE
(FR) CIRCUIT À BASE DE PORTE TROIS ÉTATS ET DE PORTE DE TRANSFERT AVEC COUVERTURE DE BALAYAGE COMPLET
Abstract
(EN)
A tristate and pass-gate based multiplexer circuit structure is described with full scan coverage capability. The circuit provides deterministic state at its output avoiding high impedance (Z) logic states in silicon. This is realized using a pull-up transistors, pull-down transistors, or through stages of combinational logic combining the multiplexer selects/enables feeding a pull-up or pull-down transistors.
(FR)
L'invention concerne une structure de circuit multiplexeur à base de porte trois états et de porte de transfert ayant une capacité de couverture de balayage complet. Le circuit fournit un état déterministe à sa sortie évitant des états logiques d'impédance élevée (Z) dans le silicium. Ceci est réalisé à l'aide de transistors d'excursion haute, de transistors d'excursion basse ou par l'intermédiaire d'étages de logique combinatoire combinant le multiplexeur qui sélectionne/permet l'alimentation de transistors d'excursion haute ou d'excursion basse.
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