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1. WO2020220666 - MANUFACTURING PROCESS FOR DIODE CHIP HAVING ELECTRODES ON SAME SIDE AND SHALLOW TRENCH

Publication Number WO/2020/220666
Publication Date 05.11.2020
International Application No. PCT/CN2019/121779
International Filing Date 28.11.2019
IPC
H01L 29/861 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
86controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861Diodes
H01L 29/06 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02Semiconductor bodies
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/329 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
328Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors
329the devices comprising one or two electrodes, e.g. diodes
H01L 23/367 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
34Arrangements for cooling, heating, ventilating or temperature compensation
36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
367Cooling facilitated by shape of device
H01L 23/373 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
34Arrangements for cooling, heating, ventilating or temperature compensation
36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
373Cooling facilitated by selection of materials for the device
H01L 23/31 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulation, e.g. encapsulating layers, coatings
31characterised by the arrangement
CPC
H01L 21/228
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; ; Interactions between two or more impurities; Redistribution of impurities
228using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes
H01L 23/291
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
29characterised by the material ; , e.g. carbon
291Oxides or nitrides or carbides, e.g. ceramics, glass
H01L 23/298
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
29characterised by the material ; , e.g. carbon
298Semiconductor material, e.g. amorphous silicon
H01L 23/3121
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
31characterised by the arrangement ; or shape
3107the device being completely enclosed
3121a substrate forming part of the encapsulation
H01L 23/3178
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
31characterised by the arrangement ; or shape
3157Partial encapsulation or coating
3178Coating or filling in grooves made in the semiconductor body
H01L 23/367
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
34Arrangements for cooling, heating, ventilating or temperature compensation ; ; Temperature sensing arrangements
36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
367Cooling facilitated by shape of device
Applicants
  • 苏州固锝电子股份有限公司 SUZHOU GOODARK ELECTRONICS CO., LTD. [CN]/[CN]
Inventors
  • 吴念博 WU, Nianbo
Agents
  • 苏州创元专利商标事务所有限公司 SUZHOU CREATOR PATENT&TRADEMARK AGENCY LTD.
Priority Data
201910358286.330.04.2019CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) MANUFACTURING PROCESS FOR DIODE CHIP HAVING ELECTRODES ON SAME SIDE AND SHALLOW TRENCH
(FR) PROCÉDÉ DE FABRICATION DE PUCE DE DIODE AYANT DES ÉLECTRODES SUR LE MÊME CÔTÉ ET UNE TRANCHÉE PEU PROFONDE
(ZH) 一种浅沟槽的电极同侧二极管芯片的制造工艺
Abstract
(EN)
A manufacturing process for a diode chip having electrodes on the same side and a shallow trench, comprising the steps of: forming a first silica film layer (2) on the surface of a silicon substrate (1); etching and removing a first region (3) of the first silica film layer (2); performing first doping on the first region (3) to form an N+ region (10); removing the first silica film layer (2), cleaning and then forming a second silica film layer (4); etching and removing a second region (5) of the second silica film layer (4) that is spaced apart from the first region (3); performing second doping on the second region (5) to form a P+ region (11); forming a trench (6) in an edge region of the N+ region (10) or the P+ region (11); removing the second silica film layer (4), cleaning and then forming a polysilicon passivation composite film layer (7); forming a glass passivation layer (8) in the trench (6); removing the polysilicon passivation composite film layer (7) on the surfaces of the first and second regions (3, 5), and exposing the N+ region (10) and the P+ region (11); and depositing a metal layer (9) on the surfaces of the N+ region (10) and the P+ region (11) to form a metal electrode. The electrodes of the diode chip are on the same side, thus the diode chip has a small volume, low costs, and excellent electrical properties.
(FR)
L'invention concerne un procédé de fabrication d'une puce de diode ayant des électrodes sur le même côté et une tranchée peu profonde, comprenant les étapes consistant à : former une première couche de film de silice (2) sur la surface d'un substrat de silicium (1) ; graver et retirer une première région (3) de la première couche de film de silice (2) ; effectuer un premier dopage sur la première région (3) pour former une région N+ (10) ; retirer la première couche de film de silice (2), nettoyer et former ensuite une seconde couche de film de silice (4) ; graver et retirer une seconde région (5) de la seconde couche de film de silice (4) qui est espacée de la première région (3) ; effectuer un second dopage sur la seconde région (5) pour former une région P+ (11) ; former une tranchée (6) dans une région de bord de la région N+ (10) ou de la région P+ (11) ; retirer la seconde couche de film de silice (4), nettoyer et former ensuite une couche de film composite de passivation de polysilicium (7) ; former une couche de passivation de verre (8) dans la tranchée (6) ; retirer la couche de film composite de passivation de polysilicium (7) sur les surfaces des première et seconde régions (3, 5), et exposer la région N+ (10) et la région P+ (11) ; et déposer une couche métallique (9) sur les surfaces de la région N+ (10) et de la région P+ (11) pour former une électrode métallique. Les électrodes de la puce de diode sont sur le même côté, de sorte que la puce de diode présente un petit volume, de faibles coûts et d'excellentes propriétés électriques.
(ZH)
一种浅沟槽的电极同侧二极管芯片的制造工艺,步骤包括:在硅片衬底(1)表面形成第一二氧化硅薄膜层(2);刻蚀并去除第一二氧化硅薄膜层(2)的一第一区域(3);对第一区域(3)进行第一掺杂形成N+区(10);将第一二氧化硅薄膜层(2)去除,清洗后形成第二二氧化硅薄膜层(4);刻蚀并去除第二二氧化硅薄膜层(4)的一第二区域(5),与第一区域(3)间隔设置;对第二区域(5)进行第二掺杂形成P+区(11);在N+区(10)或P+区(11)的边缘区域开沟槽(6);将第二二氧化硅薄膜层(4)去除,清洗并形成多晶硅钝化复合薄膜层(7);在沟槽(6)中形成玻璃钝化层(8);将第一、第二区域(3、5)表面的多晶硅钝化复合薄膜层(7)去除,裸露N+区(10)及P+区(11);在N+区(10)及P+区(11)的表面沉积金属层(9)形成金属电极。所述二极管芯片的电极同侧,体积小成本低且电性能优异。
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