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1. WO2020220664 - MANUFACTURING PROCESS FOR RECTIFICATION DIODE CHIP CAPABLE OF BEING COMBINED IN PARALLEL

Publication Number WO/2020/220664
Publication Date 05.11.2020
International Application No. PCT/CN2019/121777
International Filing Date 28.11.2019
IPC
H01L 29/861 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
86controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861Diodes
CPC
H01L 21/22
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; ; Interactions between two or more impurities; Redistribution of impurities
H01L 21/561
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
561Batch processing
H01L 23/291
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
29characterised by the material ; , e.g. carbon
291Oxides or nitrides or carbides, e.g. ceramics, glass
H01L 23/367
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
34Arrangements for cooling, heating, ventilating or temperature compensation ; ; Temperature sensing arrangements
36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
367Cooling facilitated by shape of device
H01L 29/0603
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0603characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
H01L 29/0684
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0684characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Applicants
  • 苏州固锝电子股份有限公司 SUZHOU GOODARK ELECTRONICS CO., LTD. [CN]/[CN]
Inventors
  • 吴念博 WU, Nianbo
Agents
  • 苏州创元专利商标事务所有限公司 SUZHOU CREATOR PATENT&TRADEMARK AGENCY LTD.
Priority Data
201910358368.830.04.2019CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) MANUFACTURING PROCESS FOR RECTIFICATION DIODE CHIP CAPABLE OF BEING COMBINED IN PARALLEL
(FR) PROCÉDÉ DE FABRICATION DE PUCE À DIODES DE REDRESSEMENT POUVANT ÊTRE COMBINÉES EN PARALLÈLE
(ZH) 一种可并联组合的整流二极管芯片的制造工艺
Abstract
(EN)
A manufacturing method for a rectification diode chip capable of being combined in parallel. Said method comprises the following steps: forming a lower diffusion region (2) on the lower surface of a silicon wafer substrate (1) by means of first doping; forming a silicon dioxide thin-thin-film layer (4) on both the upper surface and the lower surface of the silicon wafer substrate (1); etching and removing two spacing regions (5) of the silicon dioxide thin-film layer (4) on the upper surface; performing second doping on the two spacing regions (5), so as to form an upper diffusion region (6) in each of the two spacing regions (5), the upper diffusion regions (6) being spaced apart from the lower diffusion region (2) in the vertical direction; forming trenches (8) on edge regions of the two upper diffusion regions (6); removing the silicon dioxide thin-film layer (4) from the upper surface of the silicon wafer substrate (1), performing washing, and forming polysilicon passivation composite thin-film layers (9); forming glass passivation layers (10) in the trenches (8); removing the polysilicon passivation composite thin thin-film layers (9) from the surfaces of the two upper diffusion regions (6) to expose the two upper diffusion regions (6); at the same time, removing the silicon dioxide thin-film layer (4) from the lower surface of the silicon wafer substrate (1) to expose the lower diffusion region (2); and depositing metal layers (11) on the surfaces of the two upper diffusion regions (6) and the surface of the lower diffusion region (2) to form metal electrodes. Said method has a simple process, low costs, and high quality.
(FR)
L'invention concerne également un procédé de fabrication d'une puce à diodes de redressement pouvant être combinées en parallèle. Ledit procédé comprend les étapes suivantes : former une région de diffusion inférieure (2) sur la surface inférieure d'un substrat de tranche de silicium (1) au moyen d'un premier dopage ; former une couche de film mince de dioxyde de silicium (4) à la fois sur la surface supérieure et sur la surface inférieure du substrat de tranche de silicium (1) ; graver et retirer deux régions d'espacement (5) de la couche de film mince de dioxyde de silicium (4) sur la surface supérieure ; effectuer un second dopage sur les deux régions d'espacement (5), de façon à former une région de diffusion supérieure (6) dans chacune des deux régions d'espacement (5), les régions de diffusion supérieures (6) étant espacées de la région de diffusion inférieure (2) dans la direction verticale ; former des tranchées (8) sur des régions de bord des deux régions de diffusion supérieures (6) ; retirer la couche de film mince de dioxyde de silicium (4) de la surface supérieure du substrat de tranche de silicium (1), effectuer un lavage, et former des couches de film mince composite de passivation de polysilicium (9) ; former des couches de passivation de verre (10) dans les tranchées (8) ; retirer les couches minces de film mince composite de passivation de polysilicium (9) à partir des surfaces des deux régions de diffusion supérieures (6) pour exposer les deux régions de diffusion supérieures (6) ; en même temps, retirer la couche de film mince de dioxyde de silicium (4) de la surface inférieure du substrat de tranche de silicium (1) pour exposer la région de diffusion inférieure (2) ; et déposer des couches métalliques (11) sur les surfaces des deux régions de diffusion supérieures (6) et la surface de la région de diffusion inférieure (2) pour former des électrodes métalliques. Ledit procédé à un processus simple, des coûts bas et une haute qualité.
(ZH)
一种可并联组合的整流二极管芯片的制造方法,所述方法包括如下步骤:在硅片衬底(1)下表面通过第一掺杂形成下部扩散区(2);在硅片衬底(1)上、下表面均形成二氧化硅薄膜层(4);刻蚀并去除上表面二氧化硅薄膜层(4)的两间隔区域(5);对两所述间隔区域(5)进行第二掺杂,从而在两间隔区域(5)中分别形成一上部扩散区(6),所述上部扩散区(6)在上下方向上与所述下部扩散区(2)间隔设置;在两上部扩散区(6)的边缘区域开沟槽(8);将硅片衬底(1)上表面的二氧化硅薄膜层(4)去除,清洗并形成多晶硅钝化复合薄膜层(9);在沟槽(8)中形成玻璃钝化层(10);将两上部扩散区(6)表面的多晶硅钝化复合薄膜层(9)去除,裸露出两上部扩散区(6);同时去除硅片衬底(1)下表面的二氧化硅薄膜层(4),裸露出下部扩散区(2);在两上部扩散区(6)及下部扩散区(2)的表面沉积金属层(11)形成金属电极。上述方法工艺简单,成本低且品质高。
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