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1. WO2020220593 - BONDED SEMICONDUCTOR DEVICES HAVING PROGRAMMABLE LOGIC DEVICE AND NAND FLASH MEMORY AND METHODS FOR FORMING THE SAME

Publication Number WO/2020/220593
Publication Date 05.11.2020
International Application No. PCT/CN2019/110976
International Filing Date 14.10.2019
IPC
H01L 25/16 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
16the devices being of types provided for in two or more different main groups of groups H01L27/-H01L51/139
CPC
G11C 14/0018
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
14Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
0009in which the volatile element is a DRAM cell
0018whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
G11C 16/0483
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
0483comprising cells having several storage transistors connected in series
H01L 2224/05569
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0556Disposition
05569the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
H01L 2224/08145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
07Structure, shape, material or disposition of the bonding areas after the connecting process
08of an individual bonding area
081Disposition
0812the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
08135the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
08145the bodies being stacked
H01L 2224/32145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32135the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
32145the bodies being stacked
H01L 2224/80895
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
80001by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
808Bonding techniques
80894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
80895between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
Applicants
  • YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN]/[CN]
Inventors
  • CHENG, Weihua
  • LIU, Jun
Agents
  • NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.
Priority Data
PCT/CN2019/08523730.04.2019CN
PCT/CN2019/09744224.07.2019CN
PCT/CN2019/10529111.09.2019CN
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) BONDED SEMICONDUCTOR DEVICES HAVING PROGRAMMABLE LOGIC DEVICE AND NAND FLASH MEMORY AND METHODS FOR FORMING THE SAME
(FR) DISPOSITIFS À SEMI-CONDUCTEURS LIÉS AYANT UN DISPOSITIF LOGIQUE PROGRAMMABLE ET UNE MÉMOIRE FLASH NAND ET LEURS PROCÉDÉS DE FORMATION
Abstract
(EN)
Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.
(FR)
Selon des modes de réalisation, l’invention concerne des dispositifs à semi-conducteurs et leurs procédés de fabrication. Selon un exemple, un dispositif à semi-conducteur comprend une première structure de semi-conducteur comprenant un dispositif logique programmable, un réseau de cellules de mémoire statique à accès aléatoire (SRAM), et une première couche de liaison comprenant une pluralité de premiers contacts de liaison. Le dispositif à semi-conducteur comprend également une seconde structure à semi-conducteur comprenant des cellules de mémoire NAND et une seconde couche de liaison comprenant des seconds contacts de liaison. Le dispositif à semi-conducteur comprend en outre une interface de liaison entre la première couche de liaison et la seconde couche de liaison. Les premiers contacts de liaison sont en contact avec les seconds contacts de liaison au niveau de l’interface de liaison.
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