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1. WO2020220556 - THREE-DIMENSIONAL MEMORY DEVICE WITH THREE-DIMENSIONAL PHASE-CHANGE MEMORY

Publication Number WO/2020/220556
Publication Date 05.11.2020
International Application No. PCT/CN2019/105312
International Filing Date 11.09.2019
IPC
H01L 27/105 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
CPC
G11C 14/0018
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
14Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
0009in which the volatile element is a DRAM cell
0018whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
G11C 16/0483
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
0483comprising cells having several storage transistors connected in series
H01L 2224/05569
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0556Disposition
05569the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
H01L 2224/08145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
07Structure, shape, material or disposition of the bonding areas after the connecting process
08of an individual bonding area
081Disposition
0812the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
08135the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
08145the bodies being stacked
H01L 2224/32145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32135the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
32145the bodies being stacked
H01L 2224/80895
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
80001by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
808Bonding techniques
80894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
80895between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
Applicants
  • YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN]/[CN]
Inventors
  • LIU, Jun
Agents
  • NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.
Priority Data
PCT/CN2019/08523730.04.2019CN
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) THREE-DIMENSIONAL MEMORY DEVICE WITH THREE-DIMENSIONAL PHASE-CHANGE MEMORY
(FR) DISPOSITIF DE MÉMOIRE TRIDIMENSIONNELLE À MÉMOIRE TRIDIMENSIONNELLE DE CHANGEMENT DE PHASE
Abstract
(EN)
A three-dimensional memory device (300) with 3D phase-change memory includes a first semiconductor structure (302) including a peripheral circuit, an array of 3D PCM cells (318), and a first bonding layer (324) including a plurality of first bonding contacts (326); a second semiconductor structure (304) including an array of 3D NAND memory strings (338) and a second bonding layer (328) including a plurality of second bonding contacts (330); a bonding interface (306) between the first bonding layer (324) and the second bonding layer (328), wherein the first bonding contacts (326) are in contact with the second bonding contacts (330) at the bonding interface (306).
(FR)
L'invention concerne un dispositif de mémoire tridimensionnelle (300) doté d'une mémoire de changement de phase 3D (PCM 3D) comprenant une première structure semi-conductrice (302) comprenant un circuit périphérique, un réseau de cellules de PCM 3D (318) et une première couche de liaison (324) comprenant une pluralité de premiers contacts de liaison (326) ; une seconde structure semi-conductrice (304) comprenant un réseau de chaînes de mémoire 3D NON-ET (338) et une seconde couche de liaison (328) comprenant une pluralité de seconds contacts de liaison (330) ; une interface de liaison (306) entre la première couche de liaison (324) et la seconde couche de liaison (328), les premiers contacts de liaison (326) étant en contact avec les seconds contacts de liaison (330) au niveau de l'interface de liaison (306).
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