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1. WO2020220274 - MEMORY SYSTEM CAPABLE OF REDUCING THE READING TIME

Publication Number WO/2020/220274
Publication Date 05.11.2020
International Application No. PCT/CN2019/085219
International Filing Date 30.04.2019
IPC
G11C 7/10 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/12 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 5/14 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by group G11C11/63
14Power supply arrangements
CPC
G11C 16/24
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
24Bit-line control circuits
G11C 16/28
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
26Sensing or reading circuits; Data output circuits
28using differential sensing or reference cells, e.g. dummy cells
G11C 16/30
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
30Power supply circuits
G11C 5/14
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
14Power supply arrangements
G11C 7/1057
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
1057Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
G11C 7/12
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
Applicants
  • YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN]/[CN]
Inventors
  • CHEN, Weirong
  • TANG, Qiang
Agents
  • NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.
Priority Data
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) MEMORY SYSTEM CAPABLE OF REDUCING THE READING TIME
(FR) SYSTÈME DE MÉMOIRE CAPABLE DE RÉDUIRE LE TEMPS DE LECTURE
Abstract
(EN)
A bias circuit includes a charging current reproduce unit, a cell current reproduce unit, a current comparator, and a bit line bias generator. The charging current reproduce unit generates a charging reference voltage according to a charging current flowing through a voltage bias transistor. The cell current reproduce unit generates a cell reference voltage according to a cell current flowing through a common source transistor. The current comparator includes a first current generator for generating a replica charging current according to the charging reference voltage, and a second current generator for generating a replica cell current according to the cell reference voltage. The bit line bias generator generates a bit line bias voltage to control a page buffer for charging a bit line according to a difference between the replica charging current and the replica cell current.
(FR)
L'invention concerne un circuit de polarisation qui comprend une unité de reproduction de courant de charge, une unité de reproduction de courant de cellule, un comparateur de courant, et un générateur de polarisation de ligne de bits. L'unité de reproduction de courant de charge génère une tension de référence de charge selon un courant de charge circulant à travers un transistor de polarisation de tension. L'unité de reproduction de courant de cellule génère une tension de référence de cellule selon un courant de cellule circulant à travers un transistor de source commune. Le comparateur de courant comprend un premier générateur de courant pour générer un courant de charge de réplique selon la tension de référence de charge, et un second générateur de courant pour générer un courant de cellule de réplique selon la tension de référence de cellule. Le générateur de polarisation de ligne de bits génère une tension de polarisation de ligne de bits afin de commander un tampon de page pour charger une ligne de bits selon une différence entre le courant de charge de réplique et le courant de cellule de réplique.
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