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1. WO2020205884 - MANAGEMENT OF MULTIPLE MEMORY IN-FIELD SELF-REPAIR OPTIONS

Publication Number WO/2020/205884
Publication Date 08.10.2020
International Application No. PCT/US2020/025999
International Filing Date 31.03.2020
IPC
G11C 29/44 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
04Detection or location of defective memory elements
08Functional testing, e.g. testing during refresh, power-on self testing or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing
44Indication or identification of errors, e.g. for repair
CPC
G11C 17/16
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
17Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
14in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
16using electrically-fusible links
G11C 29/14
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
14Implementation of control logic, e.g. test mode decoders
G11C 29/42
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
38Response verification devices
42using error correcting codes [ECC] or parity check
G11C 29/4401
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
44Indication or identification of errors, e.g. for repair
4401for self repair
Applicants
  • TEXAS INSTRUMENTS INCORPORATED [US]/[US]
  • TEXAS INSTRUMENTS JAPAN LIMITED [JP]/[JP] (JP)
Inventors
  • VARADARAJAN, Devanathan
  • SINGH, Varun
Agents
  • ABRAHAM, Ebby
Common Representative
  • TEXAS INSTRUMENTS INCORPORATED
Priority Data
16/539,80513.08.2019US
62/828,54303.04.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) MANAGEMENT OF MULTIPLE MEMORY IN-FIELD SELF-REPAIR OPTIONS
(FR) GESTION D'OPTIONS D'AUTO-RÉPARATION SUR LE TERRAIN DE MÉMOIRES MULTIPLES
Abstract
(EN)
A system (100) includes a processor (102) and a memory set (130) coupled to the processor (102). The system (100) also includes a memory repair circuit (110) coupled to the memory set (130). The memory repair circuit (130) includes a first repair circuit (116) and a second repair circuit (118). The memory repair circuit (110) also includes a test controller (114) configured to select between the first repair circuit (116) and the second repair circuit (118) to perform an in-field self- repair of the memory set (130).
(FR)
L'invention concerne un système (100) qui comprend un processeur (102) et un ensemble de mémoires (130) couplé au processeur (102). Le système (100) comprend également un circuit de réparation de mémoire (110) couplé à l'ensemble de mémoires (130). Le circuit de réparation de mémoire (130) comprend un premier circuit de réparation (116) et un second circuit de réparation (118). Le circuit de réparation de mémoire (110) comprend également un contrôleur de test (114) configuré pour effectuer une sélection entre le premier circuit de réparation (116) et le second circuit de réparation (118) afin d'effectuer une auto-réparation sur le terrain de l'ensemble de mémoires (130).
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