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1. WO2020205624 - OBLIVIOUS CARRY RUNWAY REGISTERS FOR PERFORMING PIECEWISE ADDITIONS

Publication Number WO/2020/205624
Publication Date 08.10.2020
International Application No. PCT/US2020/025466
International Filing Date 27.03.2020
IPC
G06N 10/00 2019.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
10Quantum computers, i.e. computer systems based on quantum-mechanical phenomena
CPC
G06F 17/10
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
17Digital computing or data processing equipment or methods, specially adapted for specific functions
10Complex mathematical operations
G06F 7/4824
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
4824using signed-digit representation
G06F 7/5057
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
50Adding; Subtracting
505in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
5057using table look-up; using programmable logic arrays
G06F 7/72
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
60Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations ; , e.g. using difunction pulse trains, STEELE computers, phase computers
72using residue arithmetic
G06N 10/00
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
10Quantum computers, i.e. computer systems based on quantum-mechanical phenomena
G11C 11/4063
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
Applicants
  • GOOGLE LLC [US]/[US]
Inventors
  • GIDNEY, Craig
Agents
  • VALENTINO, Joseph
  • FRANZ, Paul E.
Priority Data
62/826,14229.03.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) OBLIVIOUS CARRY RUNWAY REGISTERS FOR PERFORMING PIECEWISE ADDITIONS
(FR) REGISTRES DE PISTE DE RETENUE INCONSCIENTE POUR EFFECTUER DES ADDITIONS PAR MORCEAUX
Abstract
(EN)
Methods and apparatus for piecewise addition into an accumulation register using one or more carry runway registers, where the accumulation register includes a first plurality of qubits with each qubit representing a respective bit of a first binary number and where each carry runway register includes multiple qubits representing a respective binary number. In one aspect, a method includes inserting the one or more carry runway registers into the accumulation register at respective predetermined qubit positions, respectively, of the accumulation register; initializing each qubit of each carry runway register in a plus state; applying one or more subtraction operations to the accumulation register, where each subtraction operation subtracts a state of a respective carry runway register from a corresponding portion of the accumulation register; and adding one or more input binary numbers into the accumulation register using piecewise addition.
(FR)
L'invention concerne des procédés et des appareils pour effectuer une addition par morceaux dans un registre accumulateur à l'aide d'un ou de plusieurs registres de piste de retenue, le registre accumulateur comprenant une première pluralité de bits quantiques, chaque bit quantique représentant un bit respectif d'un premier nombre binaire et chaque registre de piste de retenue comprenant de multiples bits quantiques représentant un nombre binaire respectif. Selon un aspect, un procédé consiste à insérer le ou les registres de piste de retenue dans le registre accumulateur à des positions de bit quantique prédéterminées respectives, respectivement, du registre accumulateur ; à initialiser chaque bit quantique de chaque registre de piste de retenue dans un état plus ; à appliquer une ou plusieurs opérations de soustraction au registre accumulateur, chaque opération de soustraction soustrayant un état d'un registre de piste de retenue respectif d'une partie correspondante du registre accumulateur ; et à additionner un ou plusieurs nombres binaires d'entrée dans le registre accumulateur à l'aide d'une addition par morceaux.
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