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1. WO2020205060 - MINIMUM INPUT/OUTPUT TOGGLING RATE FOR INTERFACES

Publication Number WO/2020/205060
Publication Date 08.10.2020
International Application No. PCT/US2020/017281
International Filing Date 07.02.2020
IPC
G06F 13/42 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
42Bus transfer protocol, e.g. handshake; Synchronisation
G06F 7/58 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
58Random or pseudo-random number generators
G06F 13/40 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
40Bus structure
CPC
G06F 13/20
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
20for access to input/output bus
G06F 2213/40
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2213Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
40Bus coupling
G06F 7/582
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
58Random or pseudo-random number generators
582Pseudo-random number generators
G11C 7/1006
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
Applicants
  • INTEL CORPORATION [US]/[US]
Inventors
  • LAURSEN, Soren
  • CRITCHLOW, Robert
  • DAI, Zefu
Agents
  • MUGHAL, Usman A.
Priority Data
16/369,41129.03.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) MINIMUM INPUT/OUTPUT TOGGLING RATE FOR INTERFACES
(FR) TAUX DE BASCULEMENT D'ENTRÉE/DE SORTIE MINIMAL DES INTERFACES
Abstract
(EN)
An apparatus for implementing a minimum toggle rate guarantee may comprise first, second, and third circuitries. The first circuitry may calculate a sequence of values for an internal bus inversion signal based upon a sequence of values for a plurality of internal Input/Output (IO) signals. The second circuitry may establish a sequence of values for an external bus inversion signal by selecting between the sequence of values for the internal bus inversion signal and a sequence of substantially random values. The third circuitry may set the values for a plurality of external IO signals to inverted values of the plurality of internal signals when respectively corresponding sequence of values for the external bus inversion signal have a first value, and to values of the plurality of internal signals when respectively corresponding sequence of values for the external bus inversion signal have a second value.
(FR)
Selon la présente invention, un appareil permettant de mettre en œuvre une garantie de taux de basculement minimal peut comprendre des premier, deuxième et troisième circuits. Le premier circuit peut calculer une séquence de valeurs relatives à un signal d'inversion de bus interne sur la base d'une séquence de valeurs relatives à une pluralité de signaux d'entrée/de sortie (ES) internes . Le deuxième circuit peut établir une séquence de valeurs relatives à un signal d'inversion de bus externe en choisissant entre la séquence de valeurs du signal d'inversion de bus interne et une séquence de valeurs sensiblement aléatoires. Le troisième ensemble de circuits peut régler les valeurs relatives à une pluralité de signaux ES externes à des valeurs inversées de la pluralité de signaux internes lorsqu'une séquence correspondante de valeurs relatives au signal d'inversion de bus externe a une première valeur, et à des valeurs de la pluralité de signaux internes lorsqu'une séquence correspondante de valeurs relatives au signal d'inversion de bus externe a une seconde valeur.
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