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1. WO2020200480 - SAR ADC WITH ALTERNATING LOW AND HIGH PRECISION COMPARATORS AND UNEVEN ALLOCATION OF REDUNDANCY

Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

[ EN ]

CLAIMS

What is claimed is:

1. A method (100) of performing a Successive Approximation Register, SAR, Analog to Digital Converter, ADC, process, using a SAR ADC comprising a first comparator set, each comparator in the first comparator set having substantially a same first precision and first noise level, and a second comparator set, each comparator in the second comparator set having substantially a same second precision which is greater than the first precision, and second noise level which is lower than the first noise level, the method comprising, for each analog value conversion:

performing (102) a first decision cycle using one of the first and second comparator sets against a first range, resulting in an indication of a first subrange; selecting (104) a redundancy amount for a successive decision cycle in response to whether the first decision cycle is performed using the first or second comparator set; and

performing (106) a second decision cycle immediately after the first decision cycle, using the other of the first and second comparator sets against a second range greater than the first subrange by the selected redundancy amount.

2. The method (100) of claim 1 wherein selecting (104) a redundancy amount for a successive decision cycle comprises selecting a greater redundancy amount if the first decision cycle is performed using the first comparator set than if the first decision cycle is performed using the second comparator set.

3. The method (100) of any preceding claim wherein the redundancy amount is selected to account for one or more of a DAC settling time, a comparator noise, a comparator kickback noise, and an offset mismatch between comparators.

4. The method (100) of claim 1 wherein the decision cycles are single-bit decision cycles.

5. The method (100) of claim 1 wherein at least the first and second decision cycles are multi-bit decision cycles.

6. The method (100) of claim 1 wherein the one of the first comparator set and the second comparator set is an m-bit comparator set with 2m-1 comparators and the other of the first comparator set and the second comparator set is a k-bit comparator set with 2k-1 comparators, where m¹k.

7. The method (100) of claim 1 wherein at least one of the first comparator set and the second comparator set is an m-bit comparator set with 2m-1 comparators, where m is not an integer value.

8. The method (100) of any of claims 4-7 wherein at least one of the sets of comparators forms a flash converter.

9. The method (100) of any of claims 4-7 wherein the first decision cycle is performed using the first comparator set, and the second decision cycle is performed using the second comparator set.

10. The method (100) of claim 1 further comprising performing a plurality of the last decision cycles in the ADC process using the second comparator set.

1 1. The method (100) of claim 1 wherein a plurality of the last decision cycles in the ADC process are single-bit decision cycles.

12. The method (100) of claim 1 wherein at least one decision cycle is added to the ADC process to accommodate the redundancy added to the range of the one or more decision cycles.

13. A Successive Approximation Register, SAR, Analog to Digital Converter, ADC (50), comprising:

a first comparator set (A1 , B1 , C1 ), each comparator in the first comparator set having substantially a same first precision and first noise level;

a second comparator set (A2, B2, C2), each comparator in the second comparator set having substantially a same second precision which is greater than the first precision, and second noise level which is lower than the first noise level; and SAR logic adapted to

perform (102) a first decision cycle using one of the first and second comparator sets against a first range, resulting in an indication of a first subrange; select (104) a redundancy amount for a successive decision cycle in response to whether the first decision cycle is performed using the first or second comparator set; and

perform (106) a second decision cycle immediately after the first decision cycle, using the other of the first and second comparator sets against a second range greater than the first subrange by the selected redundancy amount.

14. The SAR ADC (50) of claim 13 wherein the SAR logic (54) is adapted to select (104) a redundancy amount for a successive decision cycle by comprises selecting a greater redundancy amount if the first decision cycle is performed using the first comparator set than if the first decision cycle is performed using the second comparator set.

15. The SAR ADC (50) of any of claims 13-14 wherein the SAR logic is further adapted to select the redundancy amount to account for one or more of a DAC settling time, a comparator noise, a comparator kickback noise, and an offset mismatch between comparators.

16. The SAR ADC (50) of claim 13 wherein the decision cycles are single-bit decision cycles.

17. The SAR ADC (50) of claim 13 wherein at least the first and second decision cycles are multi-bit decision cycles.

18. The SAR ADC (50) of claim 13 wherein the one of the first comparator set and the second comparator set is an m-bit comparator set with 2m-1 comparators and the other of the first comparator set and the second comparator set is a k-bit comparator set with 2k-1 comparators, where m¹k.

19. The SAR ADC (50) of claim 13 wherein at least one of the first comparator set and the second comparator set is an m-bit comparator set with 2m-1 comparators, where m is not an integer value.

20. The SAR ADC (50) of any of claims 16-19 wherein at least one of the sets of comparators forms a flash converter.

21. The SAR ADC (50) of any of claims 16-19 wherein the SAR logic is further adapted to perform the first decision cycle using the first comparator set, and to perform the second decision cycle using the second comparator set.

22. The SAR ADC (50) of claim 13 wherein the SAR logic is further adapted to perform a plurality of the last decision cycles in the ADC process using the second comparator set.

23. The SAR ADC (50) of claim 13 wherein a plurality of the last decision cycles in the ADC process are single-bit decision cycles.

24. The SAR ADC (50) of claim 13 wherein the SAR logic is further adapted to add at least one decision cycle to the ADC process to accommodate the redundancy added to the range of the one or more decision cycles.