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1. WO2020200480 - SAR ADC WITH ALTERNATING LOW AND HIGH PRECISION COMPARATORS AND UNEVEN ALLOCATION OF REDUNDANCY

Publication Number WO/2020/200480
Publication Date 08.10.2020
International Application No. PCT/EP2019/058701
International Filing Date 05.04.2019
IPC
H03M 1/46 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
1Analogue/digital conversion; Digital/analogue conversion
12Analogue/digital converters
34Analogue value compared with reference values
38sequentially only, e.g. successive approximation type
46with digital/analogue converter for supplying reference values to converter
H03M 1/06 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
1Analogue/digital conversion; Digital/analogue conversion
06Continuously compensating for, or preventing, undesired influence of physical parameters
H03M 1/12 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
1Analogue/digital conversion; Digital/analogue conversion
12Analogue/digital converters
CPC
H03M 1/0678
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
1Analogue/digital conversion; Digital/analogue conversion
06Continuously compensating for, or preventing, undesired influence of physical parameters
0617characterised by the use of methods or means not specific to a particular type of detrimental influence
0675using redundancy
0678using additional components or elements, e.g. dummy components
H03M 1/069
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
1Analogue/digital conversion; Digital/analogue conversion
06Continuously compensating for, or preventing, undesired influence of physical parameters
0617characterised by the use of methods or means not specific to a particular type of detrimental influence
0675using redundancy
069by range overlap between successive stages or steps
H03M 1/121
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
1Analogue/digital conversion; Digital/analogue conversion
12Analogue/digital converters
1205Multiplexed conversion systems
121Interleaved, i.e. using multiple converters or converter parts for one channel
H03M 1/125
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
1Analogue/digital conversion; Digital/analogue conversion
12Analogue/digital converters
124Sampling or signal conditioning arrangements specially adapted for A/D converters
1245Details of sampling arrangements or methods
125Asynchronous, i.e. free-running operation within each conversion cycle
H03M 1/466
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
1Analogue/digital conversion; Digital/analogue conversion
12Analogue/digital converters
34Analogue value compared with reference values
38sequentially only, e.g. successive approximation type
46with digital/analogue converter for supplying reference values to converter
466using switched capacitors
Applicants
  • TELEFONAKTIEBOLAGET LM ERICSSON (PUBL) [SE]/[SE]
Inventors
  • SHARMA, Sunny
  • JONSSON, Bengt, Erik
  • SUNDSTRÖM, Lars
Agents
  • ERICSSON
Priority Data
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SAR ADC WITH ALTERNATING LOW AND HIGH PRECISION COMPARATORS AND UNEVEN ALLOCATION OF REDUNDANCY
(FR) CAN SAR AVEC COMPARATEURS DE HAUTE ET BASSE PRÉCISION ALTERNANTS ET ATTRIBUTION IRRÉGULIÈRE DE REDONDANCE
Abstract
(EN)
A Successive Approximation Register, SAR, Analog to Digital Converter, ADC, (50) achieves high speed and accuracy by (1) alternating at least some decisions between sets of comparators having different accuracy and noise characteristics, and (2) unevenly allocating redundancy (in the form of LSBs of range) for successive decisions according to the accuracy/noise of the comparator used for the preceding decision. The redundancy allocation is compensated by the addition of decision cycles. Alternating between different comparators removes the comparator reset time (treset) from the critical path, at least for those decision cycles. The uneven allocation of redundancy – specifically, allocating more redundancy to decision cycles immediately following the use of a lower accuracy/higher noise comparators – compensates for the lower accuracy and prevents the need for larger redundancy (relative to the full-scale range of a decision cycle) later in the ADC process.
(FR)
La présente invention concerne un registre d'approximations successives, SAR, convertisseur analogique-numérique, CAN, (50) qui réalise une vitesse et une précision élevées par (1) l'alternance d'au moins certaines décisions entre des ensembles de comparateurs ayant des caractéristiques de précision et de bruit différentes, et (2) l'attribution irrégulière de redondance (sous la forme de LSB de portée) pour des décisions successives en fonction de la précision/du bruit du comparateur utilisé pour la décision précédente. L'attribution de redondance est compensée par l'ajout de cycles de décision. Une alternance entre différents comparateurs élimine le temps de remise à zéro du comparateur (treset) du trajet critique, au moins pour ces cycles de décision. L'attribution irrégulière de redondance – particulièrement, l'attribution de plus de redondance à des cycles de décision immédiatement après l'utilisation d'un comparateur à plus faible précision/bruit plus important - compense pour la plus faible précision et empêche la nécessité d'une redondance plus importante (par rapport à l'échelle complète d'un cycle de décision) plus tard dans le processus CAN.
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