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1. WO2020199387 - THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATION METHODS THEREOF

Publication Number WO/2020/199387
Publication Date 08.10.2020
International Application No. PCT/CN2019/093442
International Filing Date 28.06.2019
IPC
H01L 27/1157 2017.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11568characterised by the memory core region
1157with cell select transistors, e.g. NAND
Applicants
  • YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN]/[CN]
Inventors
  • XIAO, Lihong
Agents
  • NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.
Priority Data
201910248585.129.03.2019CN
201910248601.729.03.2019CN
201910248617.829.03.2019CN
201910248966.X29.03.2019CN
201910248967.429.03.2019CN
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATION METHODS THEREOF
(FR) DISPOSITIFS DE MÉMOIRE TRIDIMENSIONNELS ET LEURS PROCÉDÉS DE FABRICATION
Abstract
(EN)
A method for forming three-dimensional (3D) memory devices includes the following operations. First, an initial channel hole (22) is formed in a stack structure (21) of a plurality first layers (211) and a plurality of second layers (212) alternatingly arranged over a substrate (10,20). An offset (224) is formed between a side surface of each one of the plurality of first layers (211) and a side surface of each one of the plurality of second layers (212) on a sidewall of the initial channel hole (22) to form a channel hole (222). A semiconductor channel (14,24) is further formed by filling the channel hole (222) with a channel-forming structure. The semiconductor channel (14,24) may have a memory layer (132) having a first memory portion surrounding a bottom of each second layer and a second memory portion connecting adjacent first memory portions. The first memory portion and the second memory portion may be staggered along a vertical direction.
(FR)
L'invention concerne un procédé de formation de dispositifs de mémoire tridimensionnels (3D) comprenant les opérations suivantes. Tout d'abord, un trou de canal initial (22) est formé dans une structure d'empilement (21) d'une pluralité de premières couches (211) et une pluralité de secondes couches (212) disposées en alternance sur un substrat (10, 20). Un décalage (224) est formé entre une surface latérale de chacune de la pluralité de premières couches (211) et une surface latérale de chacune de la pluralité de secondes couches (212) sur une paroi latérale du trou de canal initial (22) pour former un trou de canal (222). Un canal semi-conducteur (14, 24) est en outre formé par remplissage du trou de canal (222) avec une structure de formation de canal. Le canal semi-conducteur (14,24) peut avoir une couche de mémoire (132) ayant une première partie de mémoire entourant un fond de chaque seconde couche et une seconde partie de mémoire reliant des premières parties de mémoire adjacentes. La première partie de mémoire et la seconde partie de mémoire peuvent être décalées le long d'une direction verticale.
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