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1. WO2020198220 - PROCESSOR AND INTERRUPT CONTROLLER

Publication Number WO/2020/198220
Publication Date 01.10.2020
International Application No. PCT/US2020/024451
International Filing Date 24.03.2020
IPC
G06F 13/24 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
20for access to input/output bus
24using interrupt
CPC
G06F 13/26
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
20for access to input/output bus
24using interrupt
26with priority control
G06F 13/4031
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
40Bus structure
4004Coupling between buses
4027using bus bridges
4031with arbitration
G06F 9/30101
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30098Register arrangements
30101Special purpose registers
G06F 9/4818
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
48Program initiating; Program switching, e.g. by interrupt
4806Task transfer initiation or dispatching
4812by interrupt, e.g. masked
4818Priority circuits therefor
G06F 9/485
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
48Program initiating; Program switching, e.g. by interrupt
4806Task transfer initiation or dispatching
4843by program, e.g. task dispatcher, supervisor, operating system
485Task life-cycle, e.g. stopping, restarting, resuming execution
Applicants
  • ALIBABA GROUP HOLDING LIMITED
Inventors
  • ZHAO, Chaojun
  • XIANG, Xiaoyan
  • CHEN, Chen
  • ZHU, Taotao
Agents
  • CAPRON, Aaron, J.
Priority Data
201910238111.927.03.2019CN
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) PROCESSOR AND INTERRUPT CONTROLLER
(FR) PROCESSEUR ET CONTRÔLEUR D'INTERRUPTION
Abstract
(EN)
Embodiments of the present disclosure provide an interrupt controller in a processor, comprising: an interrupt sampling circuitry configured to receive one or more interrupts from one or more interrupt sources that are communicatively coupled to the interrupt controller; and an arbitration circuitry configured to select a to-be-responded interrupt from the received one or more interrupts, the arbitration circuitry comprising: a selection circuitry configured to select from the one or more interrupts a highest-priority interrupt that has a highest priority among the one or more interrupts; and a threshold comparison circuitry communicatively coupled to the selection circuitry, the threshold comparison circuitry configured to compare the priority of the highest-priority interrupt with a preset priority threshold, wherein the arbitration circuitry is configured to select the highest-priority interrupt as the to-be-responded interrupt in response to the threshold comparison circuitry determining that the priority of the highest-priority interrupt is higher than the preset priority threshold.
(FR)
Dans divers modes de réalisation, la présente invention concerne un contrôleur d'interruption dans un processeur, qui comprend : des circuits d'échantillonnage d'interruption conçus pour recevoir une ou plusieurs interruptions provenant d'une ou de plusieurs sources d'interruption qui sont couplées en communication au contrôleur d'interruption ; et des circuits d'arbitrage conçus pour sélectionner une interruption nécessitant une réponse parmi la ou les interruptions reçues, les circuits d'arbitrage comprenant : des circuits de sélection conçus pour sélectionner, parmi la ou les interruptions, l'interruption la plus prioritaire qui présente la priorité la plus élevée parmi la ou les interruptions ; et des circuits de comparaison de seuil couplés en communication aux circuits de sélection. Les circuits de comparaison de seuil sont conçus pour comparer la priorité de l'interruption la plus prioritaire à un seuil de priorité prédéfini, les circuits d'arbitrage étant conçus pour sélectionner l'interruption la plus prioritaire en tant qu'interruption nécessitant une réponse lorsque les circuits de comparaison de seuil déterminent que la priorité de l'interruption la plus prioritaire est supérieure au seuil de priorité prédéfini.
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