Processing

Please wait...

Settings

Settings

Goto Application

1. WO2020197803 - ADAPTIVE INTEGRATED PROGRAMMABLE DEVICE PLATFORM

Publication Number WO/2020/197803
Publication Date 01.10.2020
International Application No. PCT/US2020/022764
International Filing Date 13.03.2020
IPC
G06F 13/16 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
G06F 15/76 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general; Data processing equipment in general
76Architectures of general purpose stored program computers
H03K 19/007 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
007Fail-safe circuits
H03K 19/1776 2020.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02using specified components
173using elementary logic circuits as components
177arranged in matrix form
17748Structural details of configuration resources
1776for memories
CPC
G06F 13/16
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
G06F 15/7867
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
76Architectures of general purpose stored program computers
78comprising a single central processing unit
7867with reconfigurable architecture
H03K 19/007
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
007Fail-safe circuits
H03K 19/17712
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
173using elementary logic circuits as components
177arranged in matrix form
17704the logic functions being realised by the interconnection of rows and columns
17708using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
17712one of the matrices at least being reprogrammable
H03K 19/17728
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
173using elementary logic circuits as components
177arranged in matrix form
17724Structural details of logic blocks
17728Reconfigurable logic blocks, e.g. lookup tables
H03K 19/17736
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
173using elementary logic circuits as components
177arranged in matrix form
17736Structural details of routing resources
Applicants
  • XILINX, INC. [US]/[US]
Inventors
  • AHMAD, Sagheer
  • DASTIDAR, Jaideep
  • GAIDE, Brian, C.
  • NOGUERA SERRA, Juan, J.
  • SWARBRICK, Ian, A.
Agents
  • CUENOT, Kevin, T.
Priority Data
16/367,10827.03.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) ADAPTIVE INTEGRATED PROGRAMMABLE DEVICE PLATFORM
(FR) PLATEFORME DE DISPOSITIF PROGRAMMABLE INTÉGRÉE ADAPTATIVE
Abstract
(EN)
A device can include programmable logic circuitry, a processor system coupled to the programmable logic circuitry, and a network-on-chip coupled to the programmable logic circuitry and the processor system. The network-on-chip and the programmable logic circuitry can be configured to implement a plurality of independent partitions. The network-on-chip can be programmable to establish, for each of the plurality of independent partitions, user specified data paths communicatively linking a circuit block implemented in the programmable logic circuitry and the processor system. The device further can include a platform management controller that configures the programmable logic circuitry, the network-on-chip, and the processor system to implement the plurality of independent partitions.
(FR)
L'invention concerne un dispositif qui peut comprendre un circuit logique programmable, un système de processeur couplé au circuit logique programmable, et un réseau sur puce couplé au circuit logique programmable et au système de processeur. Le réseau sur puce et le circuit logique programmable peuvent être configurés pour mettre en œuvre une pluralité de partitions indépendantes. La puce réseau peut être programmable pour établir, pour chacune de la pluralité de partitions indépendantes, des chemins de données spécifiés par l'utilisateur reliant en communication un bloc de circuit mis en œuvre dans le circuit logique programmable et le système de processeur. Le dispositif peut en outre comprendre un dispositif de commande de gestion de plateforme qui configure les circuits logiques programmables, le réseau sur puce et le système de processeur pour mettre en œuvre la pluralité de partitions indépendantes.
Also published as
Latest bibliographic data on file with the International Bureau