Processing

Please wait...

Settings

Settings

Goto Application

1. WO2020197643 - INTEGRATED CIRCUIT PACKAGE WITH INTEGRATED VOLTAGE REGULATOR

Publication Number WO/2020/197643
Publication Date 01.10.2020
International Application No. PCT/US2020/016773
International Filing Date 05.02.2020
IPC
H01L 23/50 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
50for integrated circuit devices
H01L 23/538 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
538the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/525 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
525with adaptable interconnections
H01L 23/528 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
528Layout of the interconnection structure
H01L 25/065 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04the devices not having separate containers
065the devices being of a type provided for in group H01L27/78
H01L 23/31 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulation, e.g. encapsulating layers, coatings
31characterised by the arrangement
CPC
H01L 21/566
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
565Moulds
566Release layers for moulds, e.g. release layers, layers against residue during moulding
H01L 2224/0231
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
023Redistribution layers [RDL] for bonding areas
0231Manufacturing methods of the redistribution layers
H01L 2224/02373
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
023Redistribution layers [RDL] for bonding areas
0237Disposition of the redistribution layers
02373Layout of the redistribution layers
H01L 2224/02379
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
023Redistribution layers [RDL] for bonding areas
0237Disposition of the redistribution layers
02379Fan-out arrangement
H01L 2224/02381
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
023Redistribution layers [RDL] for bonding areas
0237Disposition of the redistribution layers
02381Side view
H01L 2224/0401
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
Applicants
  • ADVANCED MICRO DEVICES, INC. [US]/[US]
Inventors
  • BHAGAVAT, Milind, S.
  • AGARWAL, Rahul
  • CHENG, Chia-hao
Agents
  • KENNEDY, Brandon
Priority Data
16/367,73128.03.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) INTEGRATED CIRCUIT PACKAGE WITH INTEGRATED VOLTAGE REGULATOR
(FR) BOÎTIER DE CIRCUIT INTÉGRÉ AVEC RÉGULATEUR DE TENSION INTÉGRÉ
Abstract
(EN)
Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure (172) having a first plurality of conductor traces (l65d, l65e), a first molding layer (120) on the first RDL structure, plural conductive pillars (205a, 205b) in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure (115) on the first molding layer, the second RDL structure having a second plurality of conductor traces (l65a, 165b), and wherein some of the conductive pillars (205b, 205c) are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.
(FR)
La présente invention concerne divers dispositifs à puce à semi-conducteur et leurs procédés de fabrication. Selon un aspect, l'invention concerne un appareil qui comprend une première structure (172) de couche de redistribution (RDL) ayant une première pluralité de traces conductrices (l65d, l65e), une première couche de moulage (120) sur la première structure RDL, plusieurs piliers conducteurs (205a, 205b) dans la première couche de moulage, chacun des piliers conducteurs comprenant une première extrémité et une seconde extrémité, une seconde structure RDL (115) sur la première couche de moulage, la seconde structure RDL ayant une seconde pluralité de traces conductrices (l65a, 165b), et certains des piliers conducteurs (205b, 205c) sont électriquement connectés entre une partie de la première pluralité de traces conductrices et une partie de la seconde pluralité de traces conductrices pour fournir une première bobine d'induction.
Also published as
Latest bibliographic data on file with the International Bureau