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1. WO2020197633 - SIGNED-RFDAC ARCHITECTURES ENABLING WIDEBAND AND EFFICIENT 5G TRANSMITTERS

Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

[ EN ]

CLAIMS

What is claimed is:

1 . A radio frequency digital-to-analog converter (RFDAC) circuit comprising:

an RFDAC array circuit comprising an array of cells arranged into a plurality of segments, each segment comprising a set of cells, wherein each segment of the plurality of segments is configured to process input data signals; and wherein the RFDAC array circuit is configured to:

process an input data based on activating a set of segments of the plurality of segments, forming a set of active segments, in accordance with a local oscillator (LO) signal; and

when the sign of the input data is changed, deactivate a partially active segment of the set of active segments and activate a sign change segment within the RFDAC array circuit, in order to implement the sign change associated with the input data;

wherein the sign change segment comprises a segment within the plurality of segments of the RFDAC array circuit that is different from the set of active segments.

2. The RFDAC circuit of claim 1 , further comprising an LO circuit configured to: provide the LO signal to each segment of the set of active segments, to process input data during regular operation, and

when the sign change of the input data occurs, deactivate the LO signal to the partially active segment and provide a sign change LO signal to the sign change segment to activate the sign change segment, in order to implement the sign change associated with the input data, wherein the sign change LO signal has inverted polarity relative to the LO signal or the sign change LO is shifted by substantially 180 degrees, with respect to the LO signal.

3. The RFDAC circuit of claim 2, further comprising an input decoder circuit configured to:

provide a control data signal to the partially active segment, wherein the control data signal identifies a number of active cells within the partially active segment during regular operation; and

when the sign change of the input data occurs, provide a sign change control data signal to the sign change segment, wherein the sign change control data signal reflects the control data signal to be provided to the partially active segment after the sign change, and wherein the sign change control data signal identifies a number of active cells within the sign change segment.

4. The RFDAC circuit of any of the claims 1 -3, wherein the sign change segment comprises any segment within the RFDAC array circuit that is different from the set of active segments.

5. The RFDAC circuit of claim 4, wherein the partially active segment comprises one or more partially active segments and the sign change segment comprises one or more sign change segments.

6. The RFDAC circuit of any of the claims 1 -3, wherein the sign change segment comprises one of a dedicated negative segment and a dedicated positive segment, wherein the dedicated negative segment comprises a segment within the RFDAC array circuit configured to process only negative input data signals and wherein the dedicated negative segment comprises the sign change segment when the sign change associated with the input data comprises a positive to negative transition; and

wherein the dedicated positive segment comprises a segment within the RFDAC array circuit configured to process only positive input data signals and wherein the dedicated positive segment comprises the sign change segment when the sign change associated with the input data comprises a negative to positive transition.

7. The RFDAC circuit of any of the claims 1 -3, wherein the RFDAC array circuit is configured to deactivate the partially active segment of the set of active segments and activate the sign change segment within the RFDAC array circuit, during a predefined time interval following the sign change of the input data.

8. The RFDAC circuit of claim 7, wherein the RFDAC array circuit is further configured to deactivate the sign change segment, after the predefined time interval.

9. The RFDAC circuit of any of the claims 7-8, wherein the predefined time interval comprises half an LO period after the sign change.

10. The RFDAC circuit of any of the claims 1 -3, when each cell of the RFDAC array circuit comprises a left half circuit and a right half circuit, wherein the left half cell circuit and the right half cell circuit are driven with opposite phases of the LO signal or with LO signal phase shifted by 180 degrees.

1 1 . The RFDAC circuit of claim 10, wherein selectively deactivating the partially active segment comprises deactivating either the right half circuits or the left half circuits associated with the partially active segment that would experience a touching LO transition associated with the sign change, and activating the sign change segment comprises activating either the right half circuits or the left half circuits corresponding to the partially active segment.

12. The RFDAC circuit of any of the claims 1 -2, wherein the number of active cells within the partially active segment and the number of active cells within the sign change segment is different.

13. The RFDAC circuit of any of the claims 1 -2, wherein the input data comprises I-phase input data and Q-phase input data, and wherein processing the input data comprises:

processing the l-phase input data based on activating a set of segments of the plurality of segments of the RFDAC array circuit, forming a set of l-phase segments, in accordance with the local oscillator (LO) signal; and

processing the Q-phase input data based on activating a set of segments of the plurality of segments of the RFDAC array circuit, forming a set of Q-phase segments, in accordance with the local oscillator (LO) signal.

14. The RFDAC circuit of claim 13, wherein implementing the sign change

comprises:

deactivating a partially active segment within the set of l-phase segments and activating a l-phase sign change segment within the RFDAC array circuit, in order to implement a sign change associated with the l-phase input data, wherein the l-phase sign change segment comprises a segment within the plurality of segments within the RFDAC array circuit that is different from the set of l-phase segments and the set of Q-phase segments; and

deactivating a partially active segment within the set of Q-phase segments and activating a Q-phase sign change segment within the RFDAC array circuit, in order to implement a sign change associated with the Q-phase input data, wherein the Q-phase sign change segment comprises a segment within the plurality of segments within the RFDAC array circuit that is different from the set of Q-phase segments and the set of I-phase segments.

15. The RFDAC circuit of claim 14, wherein the control data signal provided by the input decoder circuit comprises an l-phase control data signal that identifies a number of active cells within the partially active segment of the set of active l-phase segments, and a Q-phase control data signal that identifies a number of active cells within the partially active segment of the set of active Q-phase segments.

16. The RFDAC circuit of claim 15, wherein the sign change control data signal provided by the input decoder circuit comprises an l-phase sign change control data signal that identifies a number of active cells within the l-phase sign change segment, and a Q-phase sign change control data signal that identifies a number of active cells within the Q-phase sign change segment.

17. A radio frequency digital-to-analog converter (RFDAC) circuit comprising:

an RFDAC array circuit comprising an array of cells arranged into a plurality of columns, each column comprising a set of cells, wherein each column of the plurality of columns is configured to process input data signals, and wherein the RFDAC array circuit is configured to:

process an input data based on activating one or more columns of the plurality of columns, in accordance with a predefined first filling order, when the sign of the input data is positive; and

process the input data based on activating one or more columns of the plurality of columns, in accordance with a predefined second, different, filling order, when the sign of the input data is negative;

wherein the filling order comprises a predefined order in which the plurality of columns is configured to be activated, in order to process the input data.

18. The RFDAC circuit of claim 17, wherein the predefined first filling order and the predefined second filling order differ by one or more columns.

19. The RFDAC circuit of claim 18, wherein the predefined first filling order and the predefined second filling order differ by one column, when the code variation associated with the sign change of the input data is less than one column.

20. The RFDAC circuit of any of the claims 17-19, further comprising an input decoder circuit configured to:

provide a first set of control signals to activate the one or more columns in accordance with the predefined first filling order, when the sign of the input data is positive; and

provide a second, different, set of control signals to activate the one or more columns in accordance with the predefined second filling order, when the sign of the input data is negative.

21 . A differential radio frequency digital-to-analog converter (RFDAC) circuit comprising:

a differential RFDAC array circuit comprising an array of differential cells, each differential cell comprising a first half cell circuit and a second half cell circuit, wherein the first half cell circuit and the second half cell circuit are driven by a local oscillator (LO) signal and an inverse LO signal respectively, and wherein the differential RFDAC array circuit is configured to:

process an input data based on activating the first half cell circuit and the second half cell circuit associated with a group of differential cells of the array of differential cells, simultaneously in each LO period, during regular operation;

activate a first set of half cell circuits comprising either a set of first half cell circuits or a set of second half cell circuits in an LO period preceding a sign change associated with the input data, in order to process the input data during a sign change; and

activate a second, different set of half cell circuits comprising either the set of first half cell circuits or the set of second half cell circuits that was not activated during the LO period preceding the sign change, in an LO period succeeding the sign change associated with the input data, in order to process the input data during the sign change.

22. The differential RFDAC circuit of claim 21 , wherein a number of half cell circuits in the first set of half cell circuits and a number of half cell circuits in the second set of half cell circuits is greater than a number of differential cells in the group of differential cells that are activated during regular operation.

23. The differential RFDAC circuit of claim 22, wherein the number of half cell circuits in the first set of half cell circuits and the number of half cell circuits in the second set of half cell circuits is double that of the number of different cells in the group of differential cells that are activated during regular operation.

24. The differential RFDAC circuit of any of the claims 21 -23, wherein the first half cell circuits and the second half cell circuits are activated during a first half of each LO period for positive input data, and wherein the first half cell circuits and the second half cell circuits are activated during a second half of each LO period for negative input data.

25. The RFDAC circuit of claim 24, wherein the sign change associated with the input data comprises a negative to positive sign change.

26. The differential RFDAC circuit of any of the claims 21 -23, wherein the first half cell circuits and the second half cell circuits are activated during a second half of each LO period for positive input data, and wherein the first half cell circuits and the second half cell circuits are activated during a first half of each LO period for negative input data.

27. The RFDAC circuit of claim 26, wherein the sign change associated with the input data comprises a positive to negative sign change.