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1. WO2020196522 - MODULE

Publication Number WO/2020/196522
Publication Date 01.10.2020
International Application No. PCT/JP2020/013022
International Filing Date 24.03.2020
IPC
H01L 23/00 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
H01L 23/28 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulation, e.g. encapsulating layers, coatings
H01L 25/00 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01F 27/32 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
27Details of transformers or inductances, in general
28Coils; Windings; Conductive connections
32Insulating of coils, windings, or parts thereof
H01F 27/36 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
27Details of transformers or inductances, in general
34Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
36Electric or magnetic shields or screens
Applicants
  • 株式会社村田製作所 MURATA MANUFACTURING CO., LTD. [JP]/[JP]
Inventors
  • 北爪 貴大 KITAZUME, Takahiro
  • 宮崎 大輔 MIYAZAKI, Daisuke
Agents
  • 特許業務法人深見特許事務所 FUKAMI PATENT OFFICE, P.C.
Priority Data
2019-05819826.03.2019JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) MODULE
(FR) MODULE
(JA) モジュール
Abstract
(EN)
In the present invention, a substrate (110) has a main surface (111), and each of one or more inductors (120) is disposed on the main surface (111). A resin sealing section (130) seals the one or more inductors (120) and covers the main surface (111) of the substrate (110). In plan view, a ground conductor section (140) is disposed on the outer peripheral side of the substrate (110) with respect to the entirety of the one or more inductors (120). A plurality of linear conductor sections (150) are formed on the resin sealing section (130). In plan view, the plurality of linear conductor sections (150) are disposed with gaps (151) between each other so that the one or more inductors (120) overlap with at least one of the plurality of linear conductor sections (150).
(FR)
Dans la présente invention, un substrat (110) a une surface principale (111), et chacune d'une ou de plusieurs bobines d'induction (120) est disposée sur la surface principale (111). Une section d'étanchéité en résine (130) scelle l'une ou plusieurs bobines d'induction (120) et recouvre la surface principale (111) du substrat (110). Dans une vue en plan, une section conductrice de masse (140) est disposée sur le côté périphérique externe du substrat (110) par rapport à la totalité de l'une ou plusieurs bobines d'induction (120). Une pluralité de sections conductrices linéaires (150) sont formées sur la section d'étanchéité en résine (130). Dans une vue en plan, la pluralité de sections conductrices linéaires (150) sont disposées avec des espaces (151) entre elles de telle sorte que l'une ou plusieurs bobines d'induction (120) chevauchent au moins l'une de la pluralité de sections conductrices linéaires (150).
(JA)
基板(110)は、主面(111)を有しており、1以上のインダクタ(120)の各々は、主面(111)上に配置されている。樹脂封止部(130)は、1以上のインダクタ(120)を封止するとともに基板(110)の主面(111)を覆っている。接地導体部(140)は、平面視において、1以上のインダクタ(120)の全体に対して、基板(110)の外周側に配置されている。複数の線状導体部(150)は、樹脂封止部(130)上に形成されている。平面視において、1以上のインダクタ(120)が、複数の線状導体部(150)のうちの少なくとも1つと重なるように、複数の線状導体部(150)が互いに隙間(151)を空けつつ配置されている。
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