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1. WO2020196132 - JOINED STRUCTURE

Publication Number WO/2020/196132
Publication Date 01.10.2020
International Application No. PCT/JP2020/011883
International Filing Date 18.03.2020
IPC
H01L 23/12 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
H01L 23/36 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
34Arrangements for cooling, heating, ventilating or temperature compensation
36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 23/373 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
34Arrangements for cooling, heating, ventilating or temperature compensation
36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
373Cooling facilitated by selection of materials for the device
H01L 33/62 2010.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48characterised by the semiconductor body packages
62Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H01L 21/60 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
Applicants
  • 三菱マテリアル株式会社 MITSUBISHI MATERIALS CORPORATION [JP]/[JP]
Inventors
  • 石川 史朗 ISHIKAWA Fumiaki
  • 山口 朋彦 YAMAGUCHI Tomohiko
  • 増山 弘太郎 MASUYAMA Kotaro
  • 岩田 広太郎 IWATA Koutarou
Agents
  • 松沼 泰史 MATSUNUMA Yasushi
  • 寺本 光生 TERAMOTO Mitsuo
  • 細川 文広 HOSOKAWA Fumihiro
  • 大浪 一徳 ONAMI Kazunori
Priority Data
2019-05536622.03.2019JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) JOINED STRUCTURE
(FR) STRUCTURE JOINTE
(JA) 接合構造体
Abstract
(EN)
A joined structure of the present invention is a joined structure in which a substrate having a circuit pattern and a member to be joined having an electrode terminal are joined via a conductive joining material, and is characterized by satisfying the following formula (1): SQRT(X)/SQRT(Y) ≥ 2.9209 × λ-0.141 where X represents a contact area between the circuit pattern and the conductive joining material, Y represents a contact area between the electrode terminal and the conductive joining material, and λ represents heat conductivity of the conductive joining material.
(FR)
La présente invention concerne une structure jointe qui est une structure jointe dans laquelle un substrat ayant un motif de circuit et un élément à joindre ayant une borne d'électrode sont joints par l'intermédiaire d'un matériau de jonction conducteur, et est caractérisé en ce qu'il satisfait à la formule suivante (1) : SQRT(X)/SQRT(Y) ≥ 2,9209 × λ-0.141 où X représente une zone de contact entre le motif de circuit et le matériau de jonction conducteur, Y représente une zone de contact entre la borne d'électrode et le matériau de jonction conducteur, et λ représente la conductivité thermique du matériau de jonction conducteur.
(JA)
本発明の接合構造体は、回路パターンを有する基板と、電極端子を備えた被接合部材とが導電性接合材を介して接合した接合構造体であって、前記回路パターンと前記導電性接合材との接触面積をXとし、前記電極端子と前記導電性接合材との接触面積をYとし、前記導電性接合材の熱伝導度をλとしたときに下記の式(1)を満足することを特徴とする。 SQRT(X)/SQRT(Y)≧2.9209×λ-0.141 (1)
Latest bibliographic data on file with the International Bureau