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1. WO2020195992 - METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Publication Number WO/2020/195992
Publication Date 01.10.2020
International Application No. PCT/JP2020/011323
International Filing Date 16.03.2020
IPC
H01L 21/768 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/8242 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
8239Memory structures
8242Dynamic random access memory structures (DRAM)
H01L 27/108 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
Applicants
  • 東京エレクトロン株式会社 TOKYO ELECTRON LIMITED [JP]/[JP]
Inventors
  • 吉備 和雄 KIBI, Kazuo
  • 津田 俊武 TSUDA, Toshitake
  • 鈴木 健二 SUZUKI, Kenji
Agents
  • 特許業務法人酒井国際特許事務所 SAKAI INTERNATIONAL PATENT OFFICE
Priority Data
2019-06380028.03.2019JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
(FR) PROCÉDÉ DE FABRICATION DE DISPOSITIF SEMI-CONDUCTEUR
(JA) 半導体装置の製造方法
Abstract
(EN)
This method for manufacturing a semiconductor device comprises: a hole forming step; a first embedding step; a second embedding step; and an etching step. In the hole forming step, a hole is formed in a region of an insulating film laminated on a substrate. In the first embedding step, a first conductive material is embedded in the hole to a position lower than the height of a side wall of the hole. In the second embedding step, a second conductive material is further embedded by selective growth in the hole in which the first conductive material has been embedded. In the etching step, the second conductive material is etched to form a contact pad in a position over the hole.
(FR)
L'invention concerne un procédé de fabrication d'un dispositif semi-conducteur comprenant : une étape de formation de trou ; une première étape d'incorporation ; une deuxième étape d'incorporation ; et une étape de gravure. Dans l'étape de formation de trou, un trou est formé dans une région d'un film isolant stratifié sur un substrat. Dans la première étape d'incorporation, un premier matériau conducteur est incorporé dans le trou à une position plus basse que la hauteur d'une paroi latérale du trou. Dans la deuxième étape d'incorporation, un deuxième matériau conducteur est en plus incorporé par croissance sélective dans le trou dans lequel le premier matériau conducteur a été incorporé. Dans l'étape de gravure, le deuxième matériau conducteur est gravé pour former une pastille de contact dans une position sur le trou.
(JA)
半導体装置の製造方法は、ホール形成工程と、第1の埋込工程と、第2の埋込工程と、エッチング工程とを含む。ホール形成工程では、基板上に積層された絶縁膜の領域にホールが形成される。第1の埋込工程では、ホール内に、ホールを構成する側壁の高さよりも低い位置まで第1の導電材料が埋め込まれる。第2の埋込工程では、第1の導電材料が埋め込まれたホール内に、選択成長により第2の導電材料がさらに埋め込まれる。エッチング工程では、第2の導電材料をエッチングすることにより、ホールの上方の位置にコンタクトパッドが形成される。
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