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1. WO2020193642 - CIRCUIT ARRANGEMENT FOR PREVENTING ERRONEOUS DATA TRANSMISSION VIA A BUS INTERFACE

Publication Number WO/2020/193642
Publication Date 01.10.2020
International Application No. PCT/EP2020/058387
International Filing Date 25.03.2020
IPC
G06F 11/07 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
CPC
G06F 11/0739
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
0706the processing taking place on a specific hardware platform or in a specific software environment
0736in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function
0739in a data processing system embedded in automotive or aircraft systems
G06F 11/0754
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
0751Error or fault detection not based on redundancy
0754by exceeding limits
G06F 11/0772
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
0766Error or fault reporting or storing
0772Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
G06F 11/0796
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
0796Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
Applicants
  • VITESCO TECHNOLOGIES GMBH [DE]/[DE]
Inventors
  • WUNDERLICH, Andreas
  • FISCH, Alfons
Agents
  • WALDMANN, Alexander
Priority Data
10 2019 204 176.026.03.2019DE
Publication Language German (DE)
Filing Language German (DE)
Designated States
Title
(DE) SCHALTUNGSANORDNUNG ZUM VERHINDERN DER FEHLERHAFTEN DATENÜBERTRAGUNG ÜBER EINE BUSSCHNITTSTELLE
(EN) CIRCUIT ARRANGEMENT FOR PREVENTING ERRONEOUS DATA TRANSMISSION VIA A BUS INTERFACE
(FR) SYSTÈME DE CIRCUITS DESTINÉ À EMPÊCHER LA TRANSMISSION DE DONNÉES DÉFECTUEUSE PAR LE BIAIS D’UNE INTERFACE DE BUS
Abstract
(DE)
Die Erfindung betrifft eine Schaltungsanordnung zum Verhindern der fehlerhaften Datenübertragung über eine Busschnittstelle (BUS) mit einem Mikrocontroller (MC), einem mit dem Mikrocontroller (MC) verbundenen Busschnittstellenbaustein (BT) und einer den Mikrocontroller (MC) überwachenden Überwachungseinheit (MU), wobei sowohl der Mikrocontroller (MC) als auch die Überwachungseinheit (MU) einen Abschaltausgang aufweisen, die mit je einem Eingang einer logischen UND-Schaltung (AND) verbunden sind, und wobei eine den Busschnittstellenbaustein (BT) mit einem Versorgungsspannungspotential (VDDx) verbindende Schalteinheit (SE; SR) mit dem Ausgang der UND-Schaltung (AND) verbunden ist, um im Fehlerfall den Busschnittstellenbaustein (BT) von einer Versorgungsspannung trennen zu können.
(EN)
The invention relates to a circuit arrangement for preventing erroneous data transmission via a bus interface (BUS) having a microcontroller (MC), a bus interface module (BT) connected to the microcontroller (MC) and a monitoring unit (MU) monitoring the microcontroller (MC), wherein both the microcontroller (MC) and the monitoring unit (MU) have a disconnection output, these being connected to one input each of a logic AND circuit (AND), and wherein a switching unit (SE; SR) connecting the bus interface module (BT) to a supply voltage potential (VDDx) is connected to the output of the AND circuit (AND) in order to be able to isolate the bus interface module (BT) from a supply voltage in the event of an error.
(FR)
L’invention concerne un système de circuits destiné à empêcher la transmission de données défectueuse par le biais d’une interface de bus (BUS) pourvue d’un microcontrôleur (MC), d’un module d’interface de bus (BT) connecté au microcontrôleur (MC) et d’une unité de surveillance (MU) surveillant le microcontrôleur (MC). Le microcontrôleur (MC) comme l’unité de surveillance (MU) comportent une sortie de coupure qui est connectée respectivement à une entrée d’un circuit logique ET (AND), et une unité de commutatrice (SE; SR) connectant le module d’interface de bus (BT) à un potentiel d’alimentation (VDDx) étant connectée à la sortie du circuit ET (AND), afin de pouvoir séparer le module d’interface de bus (BT) d’une tension d’alimentation en cas de défaut.
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