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1. WO2020192690 - SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Publication Number WO/2020/192690
Publication Date 01.10.2020
International Application No. PCT/CN2020/081116
International Filing Date 25.03.2020
IPC
H01L 29/778 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
778with two-dimensional charge carrier gas channel, e.g. HEMT
Applicants
  • INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD. [CN]/[CN]
Inventors
  • WONG, King Yuen
Agents
  • LEE AND LI - LEAVEN IPR AGENCY LTD.
Priority Data
201910245261.228.03.2019CN
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
Abstract
(EN)
A semiconductor device includes a substrate (10), a channel layer (12) disposed on the substrate (10), and a barrier layer (14) disposed on the channel layer (12). The semiconductor device further includes a dielectric layer (16) disposed on the barrier layer (14) and defining a first recess exposing a portion of the barrier layer (14). The semiconductor device further includes a first spacer (18a) disposed within the first recess, wherein the first spacer (18a) comprises a surface (14i) laterally connecting the dielectric layer (16) to the barrier layer (14).
(FR)
L'invention concerne un dispositif à semi-conducteur comprenant un substrat (10), une couche de canal (12) disposée sur le substrat (10), et une couche barrière (14) disposée sur la couche de canal (12). Le dispositif à semi-conducteur comprend en outre une couche diélectrique (16) disposée sur la couche barrière (14) et définissant un premier évidement exposant une partie de la couche barrière (14). Le dispositif à semi-conducteur comprend en outre un premier élément d'espacement (18a) disposé à l'intérieur du premier évidement, le premier élément d'espacement (18a) comprenant une surface (14i) reliant latéralement la couche diélectrique (16) à la couche barrière (14).
Latest bibliographic data on file with the International Bureau