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1. WO2020191612 - METHOD FOR PROGRAMMING IN NON-VOLATILE MEMORY DEVICE BY APPLYING MULTIPLE BITLINE BIAS VOLTAGES

Publication Number WO/2020/191612
Publication Date 01.10.2020
International Application No. PCT/CN2019/079667
International Filing Date 26.03.2019
IPC
G11C 16/34 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
CPC
G11C 16/0483
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
0483comprising cells having several storage transistors connected in series
G11C 16/10
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
10Programming or data input circuits
G11C 16/12
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
10Programming or data input circuits
12Programming voltage switching circuits
G11C 16/24
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
24Bit-line control circuits
G11C 16/3459
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
3436Arrangements for verifying correct programming or erasure
3454Arrangements for verifying correct programming or for detecting overprogrammed cells
3459Circuits or methods to verify correct programming of nonvolatile memory cells
Applicants
  • YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN]/[CN]
Inventors
  • LI, Haibo
  • ZHANG, Chao
  • LIN, Yanxia
Agents
  • NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.
Priority Data
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) METHOD FOR PROGRAMMING IN NON-VOLATILE MEMORY DEVICE BY APPLYING MULTIPLE BITLINE BIAS VOLTAGES
(FR) PROCÉDÉ DE PROGRAMMATION DANS UN DISPOSITIF DE MÉMOIRE NON VOLATILE PAR APPLICATION DE MULTIPLES TENSIONS DE POLARISATION DE LIGNE DE BITS
Abstract
(EN)
Programming in a non-volatile memory device includes applying at least one programming pulse to a non-volatile memory cell during a first programming loop; applying at least one programming pulse to the non-volatile memory cell during a second programming loop succeeding the first programming loop; and providing a bitline bias voltage of the non-volatile memory cell according to a result of comparing a threshold voltage of the non-volatile memory cell in the first programming loop with a low verify level and/or a high verify level of a target data state of the non-volatile memory cell and a result of comparing a threshold voltage of the non-volatile memory cell in the second programming loop with the low verify level and/or the high verify level of the target data state of the non-volatile memory cell.
(FR)
L'invention concerne la programmation dans un dispositif de mémoire non volatile qui comprend l'application d'au moins une impulsion de programmation à une cellule de mémoire non volatile pendant une première boucle de programmation ; l'application d'au moins une impulsion de programmation à la cellule de mémoire non volatile pendant une seconde boucle de programmation succédant à la première boucle de programmation ; et la fourniture d'une tension de polarisation de ligne de bits de la cellule de mémoire non volatile selon un résultat de comparaison d'une tension de seuil de la cellule de mémoire non volatile dans la première boucle de programmation avec un niveau de vérification bas et/ou un niveau de vérification élevé d'un état de données cible de la cellule de mémoire non volatile et un résultat de comparaison d'une tension de seuil de la cellule de mémoire non volatile dans la seconde boucle de programmation avec le niveau de vérification bas et/ou le niveau de vérification élevé de l'état de données cible de la cellule de mémoire non volatile.
Also published as
CN201980000551.9
Latest bibliographic data on file with the International Bureau