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1. WO2020183748 - PALLADIUM-COATED COPPER BONDING WIRE, METHOD FOR PRODUCING PALLADIUM-COATED COPPER BONDING WIRE, WIRE JUNCTION STRUCTURE USING SAME, SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING SAME

Publication Number WO/2020/183748
Publication Date 17.09.2020
International Application No. PCT/JP2019/026646
International Filing Date 04.07.2019
IPC
H01L 21/60 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 21/3205 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H01L 21/768 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
CPC
H01L 21/3205
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
H01L 21/768
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
H01L 2224/45147
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
44Structure, shape, material or disposition of the wire connectors prior to the connecting process
45of an individual wire connector
45001Core members of the connector
45099Material
451with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
45138the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
45147Copper (Cu) as principal constituent
H01L 2224/45565
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
44Structure, shape, material or disposition of the wire connectors prior to the connecting process
45of an individual wire connector
4554Coating
45565Single coating layer
H01L 2224/45664
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
44Structure, shape, material or disposition of the wire connectors prior to the connecting process
45of an individual wire connector
4554Coating
45599Material
456with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
45663the principal constituent melting at a temperature of greater than 1550°C
45664Palladium (Pd) as principal constituent
H01L 23/522
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Applicants
  • 田中電子工業株式会社 TANAKA DENSHI KOGYO K. K. [JP]/[JP]
Inventors
  • 天野 裕之 AMANO Hiroyuki
  • 安徳 優希 ANTOKU Yuki
  • 桑原 岳 KUWAHARA Takeshi
  • 市川 司 ICHIKAWA Tsukasa
  • 松澤 修 MATSUZAWA Osamu
  • 陳 ▲イ▼ CHEN Wei
Agents
  • 特許業務法人サクラ国際特許事務所 SAKURA PATENT OFFICE, P.C.
Priority Data
2019-04514312.03.2019JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) PALLADIUM-COATED COPPER BONDING WIRE, METHOD FOR PRODUCING PALLADIUM-COATED COPPER BONDING WIRE, WIRE JUNCTION STRUCTURE USING SAME, SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING SAME
(FR) FIL DE CONNEXION EN CUIVRE REVÊTU DE PALLADIUM, PROCÉDÉ DE PRODUCTION DE FIL DE CONNEXION EN CUIVRE REVÊTU DE PALLADIUM, STRUCTURE DE JONCTION DE FIL L'UTILISANT, DISPOSITIF À SEMI-CONDUCTEUR ET SON PROCÉDÉ DE PRODUCTION
(JA) パラジウム被覆銅ボンディングワイヤ、パラジウム被覆銅ボンディングワイヤの製造方法、及びこれを用いたワイヤ接合構造、半導体装置並びにその製造方法
Abstract
(EN)
A Pd-coated Cu bonding wire according to an embodiment of the present invention comprises 1.0-4.0 mass% of Pd and a total of 50 ppm by mass or less of sulfur group elements (5.0-12 ppm by mass of S, 5.0-20.0 ppm by mass of Se, and/or 15.0-50 ppm by mass of Te). The <100> crystal orientation in the crystal plane of a cross section of the wire is 15% or more, and the <111> crystal orientation is 50% or less. When a free air ball is formed on the wire and the tip part is analyzed, a Pd concentration area is observed on the surface thereof.
(FR)
Un mode de réalisation de la présente invention concerne un fil de liaison Cu revêtu de Pd qui comprend de 1,0 à 4,0 % en masse de Pd et un total de 50 ppm en masse ou moins d'éléments du groupe soufre (5,0-12 ppm en masse de S, 5,0 à 20,0 ppm en masse de Se, et/ou 15,0 à 50 ppm en masse de Te). L'orientation cristalline <100> dans le plan cristallin d'une section transversale du fil est de 15 % ou plus, et l'orientation cristalline <111> est de 50 % ou moins. Lorsqu'une bille d'air libre est formée sur le fil et que la partie de pointe est analysée, une zone de concentration de Pd est observée sur la surface de celui-ci.
(JA)
実施形態のPd被覆Cuボンディングワイヤは、1.0~4.0質量%のPd、および合計で50質量ppm以下のS族元素(5.0~12.0質量ppmのS、5.0~20.0質量ppmのSe、又は15.0~50質量ppmのTe)を有する。このワイヤ断面の結晶面における<100>方位比率が15%以上、かつ<111>方位比率が50%以下である。このワイヤにフリーエアーボールを形成して先端部分を分析したときに、その表面にPd濃化領域が観測される。
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