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1. WO2020159775 - MATRIX NORMAL/TRANSPOSE READ AND A RECONFIGURABLE DATA PROCESSOR INCLUDING SAME

Publication Number WO/2020/159775
Publication Date 06.08.2020
International Application No. PCT/US2020/014652
International Filing Date 22.01.2020
IPC
G06F 7/78 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
76Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
78for changing the order of data flow, e.g. matrix transposition, LIFO buffers; Overflow or underflow handling therefor
G06F 13/16 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
G06F 17/14 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
17Digital computing or data processing equipment or methods, specially adapted for specific functions
10Complex mathematical operations
14Fourier, Walsh or analogous domain transformations
G06F 17/16 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
17Digital computing or data processing equipment or methods, specially adapted for specific functions
10Complex mathematical operations
16Matrix or vector computation
G11C 7/10 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
CPC
G06F 12/0207
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
0207with multidimensional access, e.g. row/column, matrix
G06F 2207/4824
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2207Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
38Indexing scheme relating to groups G06F7/38 - G06F7/575
48Indexing scheme relating to groups G06F7/48 - G06F7/575
4802Special implementations
4818Threshold devices
4824Neural networks
G06F 5/08
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
5Methods or arrangements for data conversion without changing the order or content of the data handled
06for changing the speed of data flow, i.e. speed regularising ; or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor;
08having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
G06F 7/768
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
76Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
768Data position reversal, e.g. bit reversal, byte swapping
G06F 7/78
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
76Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
78for changing the order of data flow, e.g. matrix transposition, LIFO buffers; Overflow or underflow handling therefor
G11C 11/419
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming ; static; cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction
417for memory cells of the field-effect type
419Read-write [R-W] circuits
Applicants
  • SAMBANOVA SYSTEMS, INC. [US]/[US]
Inventors
  • KOEPLINGER, David Alan
  • PRABHAKAR, Raghu
  • SIVARAMAKRISHNAN, Ram
  • JACKSON, David Brian
  • LUTTRELL, Mark
Agents
  • DUNLAP, Andrew L.
  • HAYNES, Mark A.
  • BEFFEL, JR., Ernest J.
  • DURDIK, Paul A.
  • WU, Yiding
Priority Data
16/260,54829.01.2019US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) MATRIX NORMAL/TRANSPOSE READ AND A RECONFIGURABLE DATA PROCESSOR INCLUDING SAME
(FR) LECTURE NORMALE/TRANSPOSÉE DE MATRICE ET PROCESSEUR DE DONNÉES RECONFIGURABLE LA COMPRENANT
Abstract
(EN) A configurable circuit configurable according to the data width of elements of a matrix is described that includes a memory array, logic to write a matrix to the memory array having elements with a data width which can be specified using configuration data, logic for a transpose read of the matrix as-written and logic for normal read of the matrix as-written. The memory array includes first and second read ports operable in parallel. Transpose read logic and normal read logic can be coupled to the first and second read ports, respectively, allowing transpose and normal read of a matrix simultaneously.
(FR) Selon la présente invention, un circuit configurable, configurable selon la largeur de données d'éléments d'une matrice, comprend un réseau de mémoire, une logique permettant d'écrire une matrice dans le réseau de mémoire ayant des éléments dont une largeur de données peut être spécifiée à l'aide des données de configuration, d'une logique applicable à une lecture transposée de la matrice telle qu'elle est écrite et d'une logique applicable à une lecture normale de la matrice telle qu'elle est écrite. Le réseau de mémoire comprend des premier et second ports de lecture utilisables en parallèle. La logique de lecture transposée et la logique de lecture normale peuvent être couplées aux premier et second ports de lecture, respectivement, ce qui permet la lecture transposée et normale d'une matrice simultanément.
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