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1. WO2020142743 - ENHANCED READ SENSING MARGIN AND MINIMIZED VDD FOR SRAM CELL ARRAYS

Publication Number WO/2020/142743
Publication Date 09.07.2020
International Application No. PCT/US2020/012261
International Filing Date 03.01.2020
IPC
G11C 7/12 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 7/18 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
18Bit line organisation; Bit line lay-out
G11C 11/412 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
412using field-effect transistors only
G11C 11/413 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
H01L 27/11 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
11Static random access memory structures
CPC
G11C 11/412
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming ; static; cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
412using field-effect transistors only
G11C 11/419
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming ; static; cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction
417for memory cells of the field-effect type
419Read-write [R-W] circuits
G11C 7/12
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 8/08
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
08Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
G11C 8/16
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
16Multiple access memory array, e.g. addressing one storage element via at least independent addressing line groups
Applicants
  • SYNOPSYS, INC. [US]/[US]
Inventors
  • SIDDIQUI, M. Sultan, M.
  • SHARMA, Sudhir, Kumar
  • PORWAL, Saurabh
  • PANNALAL, Khatik, Bhagvan
  • KUMAR, Sudhir
Agents
  • PATEL, Rajiv, P.
  • BROWNSTONE, Daniel, R.
  • FARN, Michael, W.
  • MCNELIS, John, T.
  • AHN, Dohyun
Priority Data
16/734,20103.01.2020US
20191100056905.01.2019IN
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) ENHANCED READ SENSING MARGIN AND MINIMIZED VDD FOR SRAM CELL ARRAYS
(FR) MARGE DE DÉTECTION DE LECTURE AMÉLIORÉE ET VDD MINIMISÉE POUR DES RÉSEAUX DE CELLULES SRAM
Abstract
(EN)
A structure for an integrated circuit is disclosed for storing data. The integrated circuit includes a memory cell array of bit cells configured in a static random access memory (SRAM) architecture. The memory cell array is coupled to wordlines arranged in rows that control operations such as Read and Write operations. To enhance the read sensing margin of the SRAM configuration, the read port of a bit cell may include a wordline that drives two transistors (e.g., a PMOS and an NMOS transistor) to reduce data-dependent current leakage from a read bitline. An additional weak transistor keeper configuration may be used in the integrated circuit to compensate for current leakage from the read bitline. For example, a weak NMOS keeper that includes a sense amplifier, an inverter, and an NMOS connected to supply voltage VDD provides a path between the read bitline and VDD through the weak NMOS keeper.
(FR)
L'invention concerne une structure destinée à un circuit intégré pour stocker des données. Le circuit intégré comprend un réseau de cellules de mémoire de cellules binaires configurées dans une architecture de mémoire vive statique (SRAM). Le réseau de cellules de mémoire est couplé à des lignes de mots agencées en rangées qui commandent des opérations telles que des opérations de lecture et d'écriture. Pour améliorer la marge de détection de lecture de la configuration SRAM, le port de lecture d'une cellule binaire peut comprendre une ligne de mots qui commande deux transistors (par exemple, un PMOS et un transistor NMOS) afin de réduire une fuite de courant dépendante des données à partir d'une ligne de bits de lecture. Une configuration supplémentaire d'élément de maintien de transistor faible peut être utilisée dans le circuit intégré pour compenser une fuite de courant à partir de la ligne de bits de lecture. Par exemple, un élément de maintien NMOS faible qui comprend un amplificateur de détection, un onduleur et un NMOS connecté à la tension d'alimentation VDD fournit un chemin entre la ligne de bits de lecture et VDD à travers l'élément de maintien NMOS faible.
Also published as
Latest bibliographic data on file with the International Bureau