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1. WO2020142623 - VIRTUALIZATION OF A RECONFIGURABLE DATA PROCESSOR

Publication Number WO/2020/142623
Publication Date 09.07.2020
International Application No. PCT/US2020/012079
International Filing Date 02.01.2020
Chapter 2 Demand Filed 03.11.2020
IPC
G06F 15/78 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general; Data processing equipment in general
76Architectures of general purpose stored program computers
78comprising a single central processing unit
G06F 15/80 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general; Data processing equipment in general
76Architectures of general purpose stored program computers
80comprising an array of processing units with common control, e.g. single instruction multiple data processors
CPC
G06F 12/10
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
10Address translation
G06F 13/1668
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
1668Details of memory controller
G06F 13/4027
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
40Bus structure
4004Coupling between buses
4027using bus bridges
G06F 15/7839
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
76Architectures of general purpose stored program computers
78comprising a single central processing unit
7839with memory
G06F 15/7867
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
76Architectures of general purpose stored program computers
78comprising a single central processing unit
7867with reconfigurable architecture
G06F 15/7882
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
76Architectures of general purpose stored program computers
78comprising a single central processing unit
7867with reconfigurable architecture
7871Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
7882for self reconfiguration
Applicants
  • SAMBANOVA SYSTEMS, INC [US]/[US]
Inventors
  • GROHOSKI, Gregory Frederick
  • JAIRATH, Sumti
  • LUTTRELL, Mark
  • PRABHAKAR, Raghu
  • SIVARAMAKRISHNAN, Ram
  • SHAH, Manish K.
Agents
  • HAYNES, Mark A.
  • DUNLAP, Andrew L.
  • BEFFEL, JR., Ernest J.
  • DURDIK, Paul A.
  • WU, Yiding
Priority Data
16/239,25203.01.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) VIRTUALIZATION OF A RECONFIGURABLE DATA PROCESSOR
(FR) VIRTUALISATION D’UN PROCESSEUR DE DONNÉES RECONFIGURABLE
Abstract
(EN)
A reconfigurable data processor comprises an array of configurable units and a bus system configurable to define virtual machines. The system can partition the array of configurable units into a plurality of sets of configurable units, and block communications via the bus system between configurable units within a particular set and configurable units outside the particular set. A memory access controller can be connected to the bus system, configurable to confine access to memory outside the array of configurable units originating from within the particular set to memory space allocated to the particular.
(FR)
Selon la présente invention, un processeur de données reconfigurable comprend un réseau d'unités configurables et un système de bus configurable pour définir des machines virtuelles. Le système peut diviser le réseau d'unités configurables en une pluralité d'ensembles d'unités configurables, et bloquer des communications par l'intermédiaire du système de bus entre des unités configurables à l'intérieur d'un ensemble particulier et des unités configurables à l'extérieur de l'ensemble particulier. Un contrôleur d'accès à la mémoire peut être connecté au système de bus, et peut être configurable pour confiner l'accès à la mémoire à l'extérieur du réseau d'unités configurables en provenance de l'intérieur de l'ensemble particulier à un espace mémoire attribué à l'ensemble particulier.
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