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1. WO2020142263 - SURFACE-MOUNT INTEGRATED CIRCUIT PACKAGE WITH COATED SURFACES FOR IMPROVED SOLDER CONNECTION

Publication Number WO/2020/142263
Publication Date 09.07.2020
International Application No. PCT/US2019/067807
International Filing Date 20.12.2019
IPC
H01L 23/495 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488consisting of soldered or bonded constructions
495Lead-frames
CPC
H01L 21/4821
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
4814Conductive parts
4821Flat leads, e.g. lead frames with or without insulating supports
H01L 21/4825
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
4814Conductive parts
4821Flat leads, e.g. lead frames with or without insulating supports
4825Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
H01L 21/4842
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
4814Conductive parts
4821Flat leads, e.g. lead frames with or without insulating supports
4842Mechanical treatment, e.g. punching, cutting, deforming, cold welding
H01L 21/561
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
561Batch processing
H01L 21/565
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
565Moulds
H01L 21/78
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
Applicants
  • MICROCHIP TECHNOLOGY INCORPORATED [US]/[US]
Inventors
  • KITNARONG, Rangsun
  • NIMIBUTR, Vichanart
  • POOLSUP, Pattarapon
  • JUNJUEWONG, Chanyuth
Agents
  • SLAYDEN, Bruce, W., II
Priority Data
16/720,22019.12.2019US
16/720,26919.12.2019US
62/787,11231.12.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SURFACE-MOUNT INTEGRATED CIRCUIT PACKAGE WITH COATED SURFACES FOR IMPROVED SOLDER CONNECTION
(FR) BOÎTIER DE CIRCUIT INTÉGRÉ À MONTAGE EN SURFACE DOTÉ DE SURFACES REVÊTUES POUR UNE CONNEXION SOUDÉE AMÉLIORÉE
Abstract
(EN)
Methods are disclosed for forming flat no-leads packages (e.g., QFN packages) with soldering surfaces that are fully coated, e.g., by a tin immersion process, for improved solder connections of the packages to a PCB or other structure. The method includes forming a flat no-leads package structure including a leadframe terminal structure having an exposed top or bottom surface; forming a first coating of a first coating material (e.g., tin) on the exposed top or bottom surface; cutting through a full thickness of the leadframe terminal structure to define an exposed terminal sidewall surface; and forming a second coating of a second coating material (e.g., tin) over the full height of the exposed terminal sidewall surface. The coating (e.g., tin immersion coating) covering the full height of the leadframe terminal sidewall may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.
(FR)
L'invention concerne des procédés permettant de former des boîtiers plats sans fil (par exemple, des boîtiers QFN) avec des surfaces de soudure qui sont entièrement revêtues, par exemple, par un procédé d'immersion d'étain, pour des connexions soudées améliorées des boîtiers à une PCB ou à une autre structure. Le procédé consiste à former une structure de boîtier plat sans fil comprenant une structure de borne de grille de connexion ayant une surface supérieure ou inférieure exposée ; à former un premier revêtement d'un premier matériau de revêtement (par exemple, de l'étain) sur la surface supérieure ou inférieure exposée ; à couper au travers d'une épaisseur totale de la structure de borne de grille de connexion pour délimiter une surface de paroi latérale de borne exposée ; et à former un second revêtement d'un second matériau de revêtement (par exemple, de l'étain) sur toute la hauteur de la surface de paroi latérale de borne exposée. Le revêtement (par exemple, un revêtement par immersion d'étain) recouvrant la hauteur totale de la paroi latérale de borne de grille de connexion peut améliorer le flux de matériau de soudure, par exemple, lors d'une soudure à une carte de circuit imprimé, en vue de fournir une connexion soudée améliorée.
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