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1. WO2020142190 - CONFIGURABLE DATA PATH FOR MEMORY MODULES

Publication Number WO/2020/142190
Publication Date 09.07.2020
International Application No. PCT/US2019/066635
International Filing Date 16.12.2019
IPC
G11C 7/10 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 29/42 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
04Detection or location of defective memory elements
08Functional testing, e.g. testing during refresh, power-on self testing or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing
38Response verification devices
42using error correcting codes or parity check
CPC
G06F 11/1004
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1004to protect a block of data words, e.g. CRC or checksum
G06F 11/1048
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008in individual solid state devices
1048using arrangements adapted for a specific error detection or correction feature
G06F 11/1068
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008in individual solid state devices
1068in sector programmable memories, e.g. flash disk
G06F 13/1668
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
1668Details of memory controller
G11C 11/406
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
406Management or control of the refreshing or charge-regeneration cycles
G11C 11/40622
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
406Management or control of the refreshing or charge-regeneration cycles
40622Partial refresh of memory arrays
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • KINSLEY, Thomas, H.
Agents
  • PARKER, Paul, T.
  • ARNETT, Stephen, E.
  • COX, Tyler, S.
  • ALLBEE, Dannon
  • DUNHAM, Nicole, S.
Priority Data
16/715,18316.12.2019US
62/787,03931.12.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) CONFIGURABLE DATA PATH FOR MEMORY MODULES
(FR) CHEMIN DE DONNÉES CONFIGURABLE POUR MODULES DE MÉMOIRE
Abstract
(EN)
Systems and methods are described to enable a memory device integrated in a memory module or system to disable one or more data bits, nibbles or bytes of the memory device., The memory device can be further configured to disable error or redundancy checking associated with the disabled data bits, nibbles or bytes, to mask errors associated with the disabled data bits, nibbles or bytes, and/or to suppress the refresh of portions of a memory array associated with the disabled data bits, nibbles or bytes.
(FR)
L'invention concerne des systèmes et des procédés permettant à un dispositif de mémoire intégré dans un module de mémoire ou un système de désactiver un ou plusieurs bits, quartets ou octets de données du dispositif de mémoire. Le dispositif de mémoire peut en outre être configuré pour désactiver un contrôle d'erreur ou de redondance associé aux bits, quartets ou octets de données désactivés, pour masquer des erreurs associées aux bits, quartets ou octets de données désactivés, et/ou pour supprimer le rafraîchissement de parties d'un réseau de mémoire associé aux bits, quartets ou octets de données désactivés.
Also published as
Latest bibliographic data on file with the International Bureau