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1. WO2020141516 - INTEGRATED CIRCUIT I/O INTEGRITY AND DEGRADATION MONITORING

Publication Number WO/2020/141516
Publication Date 09.07.2020
International Application No. PCT/IL2019/051436
International Filing Date 30.12.2019
IPC
G01R 31/317 2006.1
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
317Testing of digital circuits
G01R 31/28 2006.1
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
CPC
G01R 31/2853
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
2851Testing of integrated circuits [IC]
2853Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
G01R 31/31717
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
317Testing of digital circuits
31712Input or output aspects
31717Interconnect testing
G01R 31/70
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
50Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
66Testing of connections, e.g. of plugs or non-disconnectable joints
70Testing of connections between components and printed circuit boards
G06F 13/1673
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
1668Details of memory controller
1673using buffers
H01L 2224/0401
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
H01L 2224/131
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
13of an individual bump connector
13001Core members of the bump connector
13099Material
131with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
Applicants
  • PROTEANTECS LTD. [IL]/[IL]
Inventors
  • FAYNEH, Eyal
  • LANDMAN, Evelyn
  • COHEN, Shai
  • REDLER, Guy
  • WEINTROB, Inbar
Agents
  • GASSNER, Dvir
  • GEYRA, Assaf
  • KESTEN, Dov
Priority Data
62/786,46030.12.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) INTEGRATED CIRCUIT I/O INTEGRITY AND DEGRADATION MONITORING
(FR) SURVEILLANCE D'INTÉGRITÉ ET DE DÉGRADATION DE CIRCUIT INTÉGRÉ E/S DE CIRCUIT
Abstract
(EN)
An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.
(FR)
L'invention concerne un bloc d'entrée/sortie (E/S) d'un circuit intégré (IC) à semi-conducteur, qui comprend : au moins un tampon E/S, conçu pour définir un ou plusieurs trajets de signal par rapport à une connexion à un bloc E/S distant par l'intermédiaire d'un canal de communication, chaque trajet de signal provoquant une pente de bord de signal respective; et un capteur E/S, couplé auxdits trajets de signal et conçu pour générer un signal de sortie indiquant : (a) une différence de synchronisation entre le bord de signal pour un premier trajet de signal et le bord de signal pour un second trajet de signal, et/ou (b) un paramètre de diagramme en œil pour un ou plusieurs desdits trajets de signal.
Also published as
IL284062
Latest bibliographic data on file with the International Bureau