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1. WO2020139833 - VERTICAL 3D SINGLE WORD LINE GAIN CELL WITH SHARED READ/WRITE BIT LINE

Publication Number WO/2020/139833
Publication Date 02.07.2020
International Application No. PCT/US2019/068341
International Filing Date 23.12.2019
IPC
H01L 27/108 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
CPC
G11C 11/403
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
403with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
G11C 11/4094
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
4094Bit-line management or control circuits
G11C 11/4096
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
4096Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
G11C 11/4097
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
4097Bit-line organisation, e.g. bit-line layout, folded bit lines
H01L 27/10802
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
10802comprising floating-body transistors, e.g. floating-body cells
H01L 27/10844
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
10844Multistep manufacturing methods
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • KARDA, Kamal M.
  • LIU, Haitao
  • SARPATWARI, Karthik
  • RAMASWAMY, Durai Vishak Nirmal
Agents
  • PERDOK, Monique M.
  • ARORA, Suneel / U.S. Reg. No. 42,267
  • BEEKMAN, Marvin / U.S. Reg. No. 38,377
  • BLACK, David W. / U.S. Reg. No. 42,331
  • LANG, Roger / U.S. Reg. No. 58,829
  • SCHEER, Bradley W. / U.S. Reg. No. 47,059
Priority Data
62/785,15926.12.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) VERTICAL 3D SINGLE WORD LINE GAIN CELL WITH SHARED READ/WRITE BIT LINE
(FR) CELLULE DE GAIN DE LIGNE DE MOT UNIQUE 3D VERTICALE À LIGNE DE BIT DE LECTURE/ÉCRITURE PARTAGÉE
Abstract
(EN)
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple levels of two-transistor (2T) memory cells vertically arranged above a substrate. Each 2T memory cell includes a charge storage transistor having a gate, a write transistor having a gate, a vertically extending access line, and a single bit line pair. The source or drain region of the write transistor is directly coupled to a charge storage structure of the charge storage transistor. The vertically extending access line is coupled to gates of both the charge storage transistor and the write transistor of 2T memory cells in multiple respective levels of the multiple vertically arranged levels. The vertically extending access line and the single bit line pair are used for both write operations and read operations of each of the 2T memory cells to which they are coupled.
(FR)
Certains modes de réalisation comprennent des appareils et des procédés de formation des appareils. L'un des appareils comprend de multiples niveaux de cellules de mémoire à deux transistors (2T) disposés verticalement au-dessus d'un substrat. Chaque cellule de mémoire à 2T comprend un transistor de stockage de charge ayant une grille, un transistor d'écriture ayant une grille, une ligne d'accès s'étendant verticalement et une paire de lignes de bit unique. La région de source ou de drain du transistor d'écriture est directement couplée à une structure de stockage de charge du transistor de stockage de charge. La ligne d'accès s'étendant verticalement est couplée aux grilles du transistor de stockage de charge et du transistor d'écriture de cellules de mémoire à 2T dans de multiples niveaux respectifs parmi les multiples niveaux disposés verticalement. La ligne d'accès s'étendant verticalement et la paire de lignes de bit unique sont utilisées pour des opérations d'écriture et des opérations de lecture de chacune des cellules de mémoire à 2T auxquelles elles sont couplées.
Also published as
Latest bibliographic data on file with the International Bureau