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1. WO2020139710 - VERTICAL 2-TRANSISTOR MEMORY CELL

Publication Number WO/2020/139710
Publication Date 02.07.2020
International Application No. PCT/US2019/067554
International Filing Date 19.12.2019
IPC
H01L 27/108 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
CPC
G11C 11/4023
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
402with charge regeneration individual to each memory cell, i.e. internal refresh
4023using field effect transistors
G11C 11/403
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
403with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
H01L 27/10802
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
10802comprising floating-body transistors, e.g. floating-body cells
H01L 27/10844
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
10844Multistep manufacturing methods
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • KARDA, Kamal M.
  • PULUGURTHA, Srinivas
  • LIU, Haitao
  • SARPATWARI, Karthik
  • RAMASWAMY, Durai Vishak Nirmal
Agents
  • PERDOK, Monique M.
  • ARORA, Suneel / U.S. Reg. No. 42,267
  • BEEKMAN, Marvin / U.S. Reg. No. 38,377
  • BLACK, David W. / U.S. Reg. No. 42,331
  • LANG, Roger / U.S. Reg. No. 58,829
  • SCHEER, Bradley W. / U.S. Reg. No. 47,059
Priority Data
62/785,11926.12.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) VERTICAL 2-TRANSISTOR MEMORY CELL
(FR) CELLULE DE MÉMOIRE VERTICALE À 2 TRANSISTORS
Abstract
(EN)
Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor.
(FR)
Certains modes de réalisation de l'invention comprennent des appareils et des procédés de formation d'un appareil. Un des appareils et des procédés comprend une cellule de mémoire dotée de premier et second transistors situés sur un substrat. Le premier transistor comprend une zone de canal. Le second transistor comprend une zone de canal qui est située sur la zone de canal du premier transistor et séparée électriquement de la première zone de canal. La cellule de mémoire comprend un élément de mémoire situé sur au moins un côté de la zone de canal du premier transistor. L'élément de mémoire est séparé électriquement de la zone de canal du premier transistor, et couplé électriquement au canal du second transistor.
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