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1. WO2020139700 - DETECTION OF ILLEGAL COMMANDS

Publication Number WO/2020/139700
Publication Date 02.07.2020
International Application No. PCT/US2019/067500
International Filing Date 19.12.2019
IPC
G11C 11/4078 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
4078Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells
G11C 11/406 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
406Management or control of the refreshing or charge-regeneration cycles
G11C 11/4076 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
4076Timing circuits
G11C 11/4096 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write circuits
4096Input/output data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
CPC
G06F 3/0604
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers ; , e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0602specifically adapted to achieve a particular effect
0604Improving or facilitating administration, e.g. storage management
G06F 3/0619
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers ; , e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0602specifically adapted to achieve a particular effect
0614Improving the reliability of storage systems
0619in relation to data integrity, e.g. data losses, bit errors
G06F 3/0659
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers ; , e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0628making use of a particular technique
0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
0659Command handling arrangements, e.g. command buffers, queues, command scheduling
G06F 3/0673
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers ; , e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0668adopting a particular infrastructure
0671In-line storage system
0673Single storage device
G06F 3/0688
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers ; , e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0668adopting a particular infrastructure
0671In-line storage system
0683Plurality of storage devices
0688Non-volatile semiconductor memory arrays
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • RICHTER, Michael, Dieter
  • BALB, Markus
Agents
  • HARRIS, Philip
Priority Data
16/719,89118.12.2019US
62/784,92726.12.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) DETECTION OF ILLEGAL COMMANDS
(FR) DÉTECTION DE COMMANDES ILLÉGALES
Abstract
(EN)
Methods, systems, and devices for detection of illegal commands are described. A memory device, such as a dynamic random access memory (DRAM), may receive a command from a device, such as a host device, to perform an access operation on at least one memory cell of a memory device. The memory device may determine, using a detection component, that a timing threshold associated with an operation of the memory device would be violated by performing the access operation. The memory device may refrain from executing the access operation based on determining that performing the access operation included in the command would violate the timing threshold. The memory device may transmit, to the device, an indication that performing the command would violate the timing threshold.
(FR)
L'invention concerne des procédés, des systèmes et des dispositifs destinés à la détection de commandes illégales. Un dispositif de mémoire, tel qu'une mémoire vive dynamique (DRAM), peut recevoir une commande provenant d'un dispositif, tel qu'un dispositif hôte, afin de réaliser une opération d'accès sur au moins une cellule de mémoire d'un dispositif de mémoire. Le dispositif de mémoire peut déterminer, à l'aide d'un composant de détection, qu'un seuil de temporisation associé à une opération du dispositif de mémoire serait violé par réalisation de l'opération d'accès. Le dispositif de mémoire peut s'abstenir d'exécuter l'opération d'accès sur la base de la détermination du fait que la réalisation de l'opération d'accès incluse dans la commande violerait le seuil de temporisation. Le dispositif de mémoire peut transmettre, au dispositif, une indication que la réalisation de la commande violerait le seuil de temporisation.
Also published as
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