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1. WO2020139564 - INSTRUCTION TIGHTLY-COUPLED MEMORY AND INSTRUCTION CACHE ACCESS PREDICTION

Publication Number WO/2020/139564
Publication Date 02.07.2020
International Application No. PCT/US2019/065849
International Filing Date 12.12.2019
IPC
G06F 9/38 2018.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
G06F 9/00 2018.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
G06F 13/16 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
G06F 13/40 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
40Bus structure
G06F 15/80 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general; Data processing equipment in general
76Architectures of general purpose stored program computers
80comprising an array of processing units with common control, e.g. single instruction multiple data processors
CPC
G06F 12/0862
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0862with prefetch
G06F 12/0864
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0864using pseudo-associative means, e.g. set-associative or hashing
G06F 12/0875
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0875with dedicated cache, e.g. instruction or stack
G06F 2212/1024
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
10Providing a specific technical effect
1016Performance improvement
1024Latency reduction
G06F 2212/452
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
45Caching of specific data in cache memory
452Instruction code
G06F 2212/6028
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
60Details of cache memory
6028Prefetching based on hints or prefetch instructions
Applicants
  • SIFIVE, INC. [US]/[US]
Inventors
  • ASANOVIC, Krste
  • WATERMAN, Andrew
Agents
  • BASILE, JR., Andrew, R.
  • KNIGHT, Michelle, L.
Priority Data
16/553,83928.08.2019US
62/785,94728.12.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) INSTRUCTION TIGHTLY-COUPLED MEMORY AND INSTRUCTION CACHE ACCESS PREDICTION
(FR) MÉMOIRE À COUPLAGE SERRÉ D'INSTRUCTIONS ET PRÉDICTION D'ACCÈS À UNE MÉMOIRE CACHE D'INSTRUCTIONS
Abstract
(EN)
Disclosed herein are systems and method for instruction tightly-coupled memory (iTIM) and instruction cache (iCache) access prediction. A processor may use a predictor to enable access to the iTIM or the iCache and a particular way (a memory structure) based on a location state and program counter value. The predictor may determine whether to stay in an enabled memory structure, move to and enable a different memory structure, or move to and enable both memory structures. Stay and move predictions may be based on whether a memory structure boundary crossing has occurred due to sequential instruction processing, branch or jump instruction processing, branch resolution, and cache miss processing. The program counter and a location state indicator may use feedback and be updated each instruction-fetch cycle to determine which memory structure(s) needs to be enabled for the next instruction fetch.
(FR)
L'invention porte sur des systèmes et un procédé de mémoire à couplage serré d'instructions (iTIM) et à une prédiction d'accès à une mémoire cache d'instructions (iCache). Un processeur peut utiliser un prédicteur pour activer l'accès à l'iTIM ou à l'iCache et une manière particulière (une structure de mémoire) sur la base d'un état d'emplacement et d'une valeur de compteur de programme. Le prédicteur peut déterminer s'il faut rester ou non dans une structure de mémoire activée, se déplacer vers et activer une structure de mémoire différente, ou se déplacer vers et activer les deux structures de mémoire. Les prédictions de séjour et de déplacement peuvent être basées sur le fait qu'un franchissement de limite de structure de mémoire s'est produit en raison d'un traitement séquentiel d'instructions, d'un traitement d'instructions de branchement ou de saut, d'une résolution de branchement et d'un traitement d'absence de mémoire cache. Le compteur de programme et un indicateur d'état d'emplacement peuvent utiliser une rétroaction et être mis à jour à chaque cycle d'extraction d'instruction afin de déterminer quelle(s) structure(s) de mémoire doi(ven)t être activée(s) pour l'extraction d'instructions suivantes.
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