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1. WO2020139424 - THREE-DIMENSIONAL MEMORY DEVICES HAVING A MULTI-STACK BONDED STRUCTURE USING A LOGIC DIE AND MULTIPLE THREE-DIMENSIONAL MEMORY DIES AND METHOD OF MAKING THE SAME

Publication Number WO/2020/139424
Publication Date 02.07.2020
International Application No. PCT/US2019/049028
International Filing Date 30.08.2019
IPC
H01L 23/00 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
G11C 16/04 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
G11C 16/08 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
08Address circuits; Decoders; Word-line control circuits
H01L 25/065 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04the devices not having separate containers
065the devices being of a type provided for in group H01L27/78
CPC
G11C 5/063
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
06Arrangements for interconnecting storage elements electrically, e.g. by wiring
063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
H01L 25/0657
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; ; Multistep manufacturing processes thereof
03all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
04the devices not having separate containers
065the devices being of a type provided for in group H01L27/00
0657Stacked arrangements of devices
H01L 25/18
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; ; Multistep manufacturing processes thereof
18the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L51/00
H01L 25/50
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; ; Multistep manufacturing processes thereof
50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
H01L 27/0688
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
06including a plurality of individual components in a non-repetitive configuration
0688Integrated circuits having a three-dimensional layout
H01L 27/11519
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
11519characterised by the top-view layout
Applicants
  • SANDISK TECHNOLOGIES LLC [US]/[US]
Inventors
  • TOTOKI, Yuji
  • INOUE, Shigehisa
  • KASAI, Yuki
  • MATSUOKA, Hironori
Agents
  • RADOMSKY, Leon
  • COHN, Joanna
  • CONNOR, David
  • GAYOSO, Tony
  • GILL, Matthew
  • GUNNELS, Zarema
  • HANSEN, Robert
  • HUANG, Stephen
  • HYAMS, David
  • JOHNSON, Timothy
  • MAZAHERY, Benjamin
  • MURPHY, Timothy
  • NORRIS, Christine
  • O'BRIEN, Michelle
  • PARK, Byeongju
  • RUTT, Steven
  • SULSKY, Martin
Priority Data
16/231,75224.12.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) THREE-DIMENSIONAL MEMORY DEVICES HAVING A MULTI-STACK BONDED STRUCTURE USING A LOGIC DIE AND MULTIPLE THREE-DIMENSIONAL MEMORY DIES AND METHOD OF MAKING THE SAME
(FR) DISPOSITIFS DE MÉMOIRE TRIDIMENSIONNELLE PRÉSENTANT UNE STRUCTURE LIÉE À EMPILEMENT MULTIPLE AU MOYEN D'UNE PUCE LOGIQUE ET DE MULTIPLES PUCES DE MÉMOIRE TRIDIMENSIONNELLE, ET LEUR PROCÉDÉ DE FABRICATION
Abstract
(EN)
A first memory die including an array of first memory stack structures and a logic die including a complementary metal oxide semiconductor (CMOS) circuit are bonded. The CMOS circuit includes a first peripheral circuitry electrically coupled to nodes of the array of first memory stack structures through a first subset of first metal interconnect structures included within the first memory die. A second memory die is bonded to the first memory die. The second memory die includes an array of second memory stack structures. The CMOS circuit includes a second peripheral circuitry electrically coupled to nodes of the array of second memory stack structures through a second subset of first metal interconnect structures included within the first memory die and through second metal interconnect structures included within the second memory die. The logic die provides peripheral devices that support operation of memory stack structures in multiple memory dies.
(FR)
Selon la présente invention, une première puce de mémoire comprenant un réseau de premières structures d'empilement de mémoire et une puce logique comprenant un circuit à semi-conducteur complémentaire à l'oxyde de métal (CMOS) sont liées. Le circuit CMOS comprend une première circuiterie périphérique couplée électriquement à des nœuds du réseau de premières structures d'empilement de mémoire par l'intermédiaire d'un premier sous-ensemble de premières structures d'interconnexion métalliques comprises dans la première puce de mémoire. Une seconde puce de mémoire est liée à la première puce de mémoire. La seconde puce de mémoire est pourvue d'un réseau de secondes structures d'empilement de mémoire. Le circuit CMOS comprend une seconde circuiterie périphérique couplée électriquement à des nœuds du réseau de secondes structures d'empilement de mémoire par l'intermédiaire d'un second sous-ensemble de premières structures d'interconnexion métalliques comprises dans la première puce de mémoire et par l'intermédiaire de secondes structures d'interconnexion métalliques comprises dans la seconde puce de mémoire. La puce logique offre des dispositifs périphériques qui permettent le fonctionnement de structures d'empilement de mémoire dans de multiples puces de mémoire.
Also published as
Latest bibliographic data on file with the International Bureau