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1. WO2020139422 - AN APPARATUS WITH A ROW-HAMMER ADDRESS LATCH MECHANISM

Publication Number WO/2020/139422
Publication Date 02.07.2020
International Application No. PCT/US2019/045056
International Filing Date 05.08.2019
IPC
G11C 11/4091 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write circuits
4091Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
G11C 11/408 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
408Address circuits
G11C 11/406 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
406Management or control of the refreshing or charge-regeneration cycles
CPC
G06F 12/0646
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
0646Configuration or reconfiguration
G06F 2212/1008
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
10Providing a specific technical effect
1008Correctness of operation, e.g. memory ordering
G11C 11/406
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
406Management or control of the refreshing or charge-regeneration cycles
G11C 11/40611
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
406Management or control of the refreshing or charge-regeneration cycles
40611External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
G11C 11/408
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
408Address circuits
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • OKUMA, Sadayuki
Agents
  • PARKER, Paul, T.
  • DUNHAM, Nicole, D.
  • ALLBEE, Dannon
  • ARNETT, Stephen, E.
  • COX, Tyler, S.
Priority Data
16/234,39727.12.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) AN APPARATUS WITH A ROW-HAMMER ADDRESS LATCH MECHANISM
(FR) APPAREIL DOTÉ D'UN MÉCANISME DE VERROUILLAGE D'ADRESSE D'ATTAQUES RÉPÉTÉES
Abstract
(EN)
An apparatus includes an address bus configured to convey a command address; a primary address latch connected to the address bus and configured to latch a first address; a primary counter connected to the primary address latch and configured to track a primary count value when the command address matches the first address; and a secondary counter connected to the primary counter and configured to update a secondary count value when the primary count value reaches a primary threshold.
(FR)
L'invention concerne un appareil qui comprend un bus d'adresse configuré pour transporter une adresse de commande; un verrou d'adresse primaire connecté au bus d'adresse et configuré pour verrouiller une première adresse; un compteur primaire connecté au verrou d'adresse primaire et configuré pour suivre une valeur de comptage primaire lorsque l'adresse de commande correspond à la première adresse; et un compteur secondaire connecté au compteur principal et configuré pour mettre à jour une valeur de comptage secondaire lorsque la valeur de comptage primaire atteint un seuil primaire.
Also published as
Latest bibliographic data on file with the International Bureau