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1. WO2020138663 - DEVICE FOR RISC-V-BASED OPERATION INCLUDING HARDWARE-BASED FAST OPERATION SUPPORTING USER-DEFINED INSTRUCTION SET, AND METHOD THEREFOR

Publication Number WO/2020/138663
Publication Date 02.07.2020
International Application No. PCT/KR2019/013045
International Filing Date 04.10.2019
IPC
G06F 9/38 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
G06F 9/30 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
CPC
G06F 9/30079
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30076to perform miscellaneous control operations, e.g. NOP
30079Pipeline control instructions
G06F 9/30145
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30145Instruction analysis, e.g. decoding, instruction word fields
G06F 9/382
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3818Decoding for concurrent execution
382Pipelined decoding, e.g. using predecoding
G06F 9/3867
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3867using instruction pipelines
G06F 9/3885
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3885using a plurality of independent parallel functional units
Applicants
  • (주)자람테크놀로지 ZARAM TECHNOLOGY CO., LTD. [KR]/[KR]
Inventors
  • 이태종 LEE, Tae Jong
  • 박성훈 PARK, Sung Hoon
  • 서인식 SEO, In Shik
  • 백준현 BAEK, Joon Hyun
Agents
  • 전종학 JEON, Jonghag
Priority Data
10-2018-016930126.12.2018KR
Publication Language Korean (KO)
Filing Language Korean (KO)
Designated States
Title
(EN) DEVICE FOR RISC-V-BASED OPERATION INCLUDING HARDWARE-BASED FAST OPERATION SUPPORTING USER-DEFINED INSTRUCTION SET, AND METHOD THEREFOR
(FR) DISPOSITIF POUR OPÉRATION FONDÉE SUR RISC-V COMPRENANT UNE OPÉRATION RAPIDE FONDÉE SUR MATÉRIEL PRENANT EN CHARGE UN ENSEMBLE D'INSTRUCTIONS DÉFINI PAR L'UTILISATEUR ET PROCÉDÉ ASSOCIÉ
(KO) 사용자 정의 명령어 셋을 지원하는 하드웨어 고속 연산 결합형 RISC-V 기반 연산 장치 및 그 방법
Abstract
(EN)
The present invention relates to a device for RISC-V-based operation including hardware-based fast operation supporting a user-defined instruction set, and a method therefor, wherein a hardware-based fast operation unit executing user-defined functions, along with a RISC-V-based operation device, is formed as a single chip through a field programmable gate array (FPGA), and normal operations and user-defined operations are performed at instruction level through a program using a RISC-V basic instruction set including a user-defined instruction set, rather than performed using special bus connection architecture, and the user-defined instruction set and corresponding functions can be freely changed to provide flexibility. The device makes it possible to implement a special purpose operation unit at instruction level without developing any dedicated ASIC using special purpose operations, etc. requiring conventional dedicated hardware, by performing "modification to a new processor architecture having a new ISA that is suitable for particular purposes" as in the way of conventional firmware updating that modifies only software configuration except for hardware configuration.
(FR)
La présente invention concerne un dispositif pour une opération fondée sur RISC-V comprenant une opération rapide fondée sur le matériel prenant en charge un ensemble d'instructions défini par l'utilisateur, et un procédé associé. Une unité d'opération rapide fondée sur le matériel exécutant des fonctions définies par l'utilisateur, conjointement avec un dispositif d'opération fondé sur RISC-V, est constituée sous la forme d'une puce unique par l'intermédiaire d'une matrice prédiffusée programmable par l'utilisateur (FPGA), et des opérations normales et des opérations définies par l'utilisateur sont effectuées au niveau de l'instruction par l'intermédiaire d'un programme à l'aide d'un ensemble d'instructions de base RISC-V comprenant un ensemble d'instructions défini par l'utilisateur, plutôt qu'être effectuées à l'aide d'une architecture de connexion de bus spéciale, et l'ensemble d'instructions défini par l'utilisateur et les fonctions correspondantes peuvent être changés librement pour assurer la flexibilité. Le dispositif permet de mettre en œuvre une unité d'opération à usage spécial au niveau de l'instruction sans développer aucun ASIC dédié à l'aide d'opérations à usage spécial, etc. nécessitant un matériel spécialisé classique, en effectuant une « modification sur une nouvelle architecture de processeur présentant une nouvelle ISA qui est appropriée à des fins particulières » comme dans le mode de mise à jour de micrologiciel classique qui ne modifie que la configuration logicielle à l'exception de la configuration matérielle.
(KO)
본 발명은 FPGA(Field Programmable Gate Array)를 통해 사용자 정의 기능을 실행하는 하드웨어 고속 연산부를 RISC-V 기반 연산 장치와 함께 단일 칩으로 구성하고, 사용자 정의 명령어 셋을 포함하는 RISC-V 기본 명령어 셋을 이용한 프로그램을 통해 별도의 버스 연결 구성이 아닌 명령어 레벨에서 일반 연산과 사용자 정의 연산을 수행하도록 하되, 사용자 정의 명령어 셋과 대응 기능을 임의적으로 변경할 수 있는 유연성을 제공하는 사용자 정의 명령어 셋을 지원하는 하드웨어 고속 연산 결합형 RISC-V 기반 연산 장치 및 그 방법에 관한 것으로, 하드웨어 구성이 아닌 소프트웨어 구성만 변경하는 기존의 펌웨어 갱신과 같은 유사한 방식으로 '특정 용도에 적합한 새로운 ISA를 가지는 새로운 프로세서 구조변경'을 수행하여 기존 전용하드웨어가 필요한 특수 목적 연산 등을 사용하는 전용 ASIC 개발을 하지 않고도 명령어 레벨에서 특수 목적 연산부 구현이 가능한 효과가 있다.
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