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1. WO2020137341 - NONVOLATILE LOGIC CIRCUIT

Publication Number WO/2020/137341
Publication Date 02.07.2020
International Application No. PCT/JP2019/046590
International Filing Date 28.11.2019
IPC
H01L 43/08 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
08Magnetic-field-controlled resistors
H01L 21/8239 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
8239Memory structures
H01L 27/105 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
H03K 19/18 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02using specified components
18using galvano-magnetic devices, e.g. Hall-effect devices
G11C 11/16 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
02using magnetic elements
16using elements in which the storage effect is based on magnetic spin effect
CPC
G11C 11/16
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
02using magnetic elements
16using elements in which the storage effect is based on magnetic spin effect
H01L 21/8239
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology ; , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
8239Memory structures
H01L 27/105
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
H01L 43/08
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
08Magnetic-field-controlled resistors
H03K 19/18
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
18using galvano-magnetic devices, e.g. Hall-effect devices
Applicants
  • 国立大学法人東北大学 TOHOKU UNIVERSITY [JP]/[JP]
Inventors
  • 夏井 雅典 NATSUI Masanori
  • 羽生 貴弘 HANYU Takahiro
  • 遠藤 哲郎 ENDOH Tetsuo
Agents
  • 特許業務法人ドライト国際特許事務所 DORAIT IP LAW FIRM
Priority Data
2018-24119125.12.2018JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) NONVOLATILE LOGIC CIRCUIT
(FR) CIRCUIT LOGIQUE NON VOLATIL
(JA) 不揮発性論理回路
Abstract
(EN)
Provided is a nonvolatile logic circuit that uses the non-complementarity of a pair of variable-resistance memory elements to achieve enhanced functionality without an increase in circuit scale. A nonvolatile logic circuit (10) that comprises: a memory part (12) that has a pair of variable-resistance memory elements (a pair of MTJ elements) (M1 and M2); a computation part (11) that is connected to the memory part (12) and performs a computation that is based on input signals (in1 and in2) and logic values that correspond to the resistances of the pair of MTJ elements (M1 and M2); a determination circuit (3) that determines whether the resistances of the pair of MTJ elements (M1 and M2) are complementary or non-complementary; and an output circuit (2) that is connected to the computation part (11) and the determination circuit (3) and outputs signals (out1 and out2) that correspond to the results of the computation performed by the computation part (11) or signals (out1 and out2) that correspond to the results of the determination made by the determination circuit (3).
(FR)
Circuit logique non volatil qui utilise la non-complémentarité d'une paire d'éléments de mémoire à résistance variable pour obtenir une fonctionnalité améliorée sans augmentation de l'échelle de circuit. Un circuit logique non volatil (10) qui comprend : une partie de mémoire (12) qui comporte une paire d'éléments de mémoire à résistance variable (une paire d'éléments MTJ) (M1 et M2) ; une partie de calcul (11) qui est connectée à la partie de mémoire (12) et effectue un calcul qui est basé sur des signaux d'entrée (in1 et in2) et des valeurs logiques qui correspondent aux résistances de la paire d'éléments MTJ (M1 et M2) ; un circuit de détermination (3) qui détermine si les résistances de la paire d'éléments MTJ (M1 et M2) sont complémentaires ou non complémentaires ; et un circuit de sortie (2) qui est connecté à la partie de calcul (11) et au circuit de détermination (3) et délivre des signaux (out1 et out2) qui correspondent aux résultats du calcul effectué par la partie de calcul (11) ou des signaux (out1 et out2) qui correspondent aux résultats de la détermination effectuée par le circuit de détermination (3).
(JA)
一対の抵抗変化型記憶素子の非相補状態を利用することで、回路規模を大きくすることなく機能の高度化を実現する不揮発性論理回路を提供する。不揮発性論理回路(10)は、一対の抵抗変化型記憶素子(一対のMTJ素子)(M1及びM2)を有する記憶部(12)と、記憶部(12)に接続され、入力信号(in1及びin2)と、一対のMTJ素子(M1及びM2)の抵抗に対応する論理値とに基づく演算を実行する演算部(11)と、一対のMTJ素子(M1及びM2)の抵抗が相補状態にあるか非相補状態にあるかを判別する判別回路(3)と、演算部(11)及び判別回路(3)に接続され、演算部(11)による演算結果に対応する信号(out1及びout2)又は判別回路(3)による判別結果に対応する信号(out1及びout2)を出力する出力回路(2)と、を備える。
Also published as
JP2020562967
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