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1. WO2020137194 - SEMICONDUCTOR WAFER EVALUATION METHOD AND MANUFACTURING METHOD AND SEMICONDUCTOR WAFER MANUFACTURING PROCESS MANAGEMENT METHOD

Publication Number WO/2020/137194
Publication Date 02.07.2020
International Application No. PCT/JP2019/044039
International Filing Date 11.11.2019
IPC
G01N 21/956 2006.1
GPHYSICS
01MEASURING; TESTING
NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
21Investigating or analysing materials by the use of optical means, i.e. using infra-red, visible or ultra-violet light
84Systems specially adapted for particular applications
88Investigating the presence of flaws, defects or contamination
95characterised by the material or shape of the object to be examined
956Inspecting patterns on the surface of objects
H01L 21/66 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
66Testing or measuring during manufacture or treatment
CPC
G01N 21/956
GPHYSICS
01MEASURING; TESTING
NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
21Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
84Systems specially adapted for particular applications
88Investigating the presence of flaws or contamination
95characterised by the material or shape of the object to be examined
956Inspecting patterns on the surface of objects
Applicants
  • 株式会社SUMCO SUMCO CORPORATION [JP]/[JP]
Inventors
  • 長澤 崇裕 NAGASAWA Takahiro
  • 村上 雅大 MURAKAMI Masahiro
Agents
  • 特許業務法人特許事務所サイクス SIKS & CO.
Priority Data
2018-24544827.12.2018JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR WAFER EVALUATION METHOD AND MANUFACTURING METHOD AND SEMICONDUCTOR WAFER MANUFACTURING PROCESS MANAGEMENT METHOD
(FR) PROCÉDÉ D'ÉVALUATION DE TRANCHE DE SEMI-CONDUCTEUR ET PROCÉDÉ DE FABRICATION ET PROCÉDÉ DE GESTION DE PROCESSUS DE FABRICATION DE TRANCHE DE SEMI-CONDUCTEUR
(JA) 半導体ウェーハの評価方法および製造方法ならびに半導体ウェーハの製造工程管理方法
Abstract
(EN)
Provided is a method for evaluating a semiconductor wafer having a polished surface. This semiconductor wafer evaluation method includes a cleaning step for cleaning the semiconductor wafer in one or more types of cleaning liquid and also includes the measurement of an LPD on the polished surface using a laser surface inspection device before and after the cleaning step and the use of the measurement results obtained through the measurement to determine the type of defect or abnormality measured as the LPD according to the determination standards indicated in table A.
(FR)
L'invention concerne un procédé d'évaluation d'une tranche de semi-conducteur ayant une surface polie. Ce procédé d'évaluation de tranche de semi-conducteur comprend une étape de nettoyage pour nettoyer la tranche de semi-conducteur dans un ou dans plusieurs types de liquide de nettoyage et comprend également l'étape de mesure d'un LPD sur la surface polie à l'aide d'un dispositif d'inspection de surface au laser avant et après l'étape de nettoyage et l'utilisation des résultats de mesure obtenus par la mesure pour déterminer le type de défaut ou d'anomalie mesuré en tant que LPD selon les normes de détermination indiquées dans le tableau A.
(JA)
研磨面を有する半導体ウェーハの評価方法であって、上記半導体ウェーハを一種以上の洗浄液により洗浄する洗浄工程を含み、上記洗浄工程の前と後にそれぞれレーザー表面検査装置を用いて上記研磨面のLPDを測定し、上記測定により得られた測定結果に基づき表Aに示す判別基準により、LPDとして測定された欠陥または異物の種類を判別することを含む半導体ウェーハの評価方法が提供される。
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