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1. WO2020137186 - WAFER MANUFACTURING METHOD AND WAFER

Publication Number WO/2020/137186
Publication Date 02.07.2020
International Application No. PCT/JP2019/043881
International Filing Date 08.11.2019
IPC
B24B 1/00 2006.1
BPERFORMING OPERATIONS; TRANSPORTING
24GRINDING; POLISHING
BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
1Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes
B24B 9/00 2006.1
BPERFORMING OPERATIONS; TRANSPORTING
24GRINDING; POLISHING
BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
9Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor
B24B 37/08 2012.1
BPERFORMING OPERATIONS; TRANSPORTING
24GRINDING; POLISHING
BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
37Lapping machines or devices; Accessories
04designed for working plane surfaces
07characterised by the movement of the work or lapping tool
08for double side lapping
B24B 37/10 2012.1
BPERFORMING OPERATIONS; TRANSPORTING
24GRINDING; POLISHING
BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
37Lapping machines or devices; Accessories
04designed for working plane surfaces
07characterised by the movement of the work or lapping tool
10for single side lapping
H01L 21/304 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
304Mechanical treatment, e.g. grinding, polishing, cutting
CPC
B24B 1/00
BPERFORMING OPERATIONS; TRANSPORTING
24GRINDING; POLISHING
BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING
1Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes
B24B 37/08
BPERFORMING OPERATIONS; TRANSPORTING
24GRINDING; POLISHING
BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING
37Lapping machines or devices; Accessories
04designed for working plane surfaces
07characterised by the movement of the work or lapping tool
08for double side lapping
B24B 37/10
BPERFORMING OPERATIONS; TRANSPORTING
24GRINDING; POLISHING
BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING
37Lapping machines or devices; Accessories
04designed for working plane surfaces
07characterised by the movement of the work or lapping tool
10for single side lapping
B24B 9/00
BPERFORMING OPERATIONS; TRANSPORTING
24GRINDING; POLISHING
BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING
9Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor
H01L 21/304
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
302to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
304Mechanical treatment, e.g. grinding, polishing, cutting
Applicants
  • 株式会社SUMCO SUMCO CORPORATION [JP]/[JP]
Inventors
  • 鳥居 勘太郎 TORII Kantarou
Agents
  • 特許業務法人樹之下知的財産事務所 KINOSHITA & ASSOCIATES
Priority Data
2018-24530127.12.2018JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) WAFER MANUFACTURING METHOD AND WAFER
(FR) PROCÉDÉ DE FABRICATION DE TRANCHE, ET TRANCHE
(JA) ウェーハの製造方法およびウェーハ
Abstract
(EN)
This method for manufacturing a wafer having a notch part is provided with: a both side polishing step for polishing both main surfaces of a wafer; a notched mirror surface polishing step for performing mirror polishing on a notch-chamfered section of the notch part; an outer peripheral mirror surface polishing step for performing mirror surface polishing on the outer peripheral chamfered section of the outer peripheral section of the wafer; and a finish polishing step for performing finish polishing on one main surface of the wafer, wherein the finish polishing step is performed after performing the notched mirror surface polishing step, the both side polishing step, and the outer peripheral mirror surface polishing step.
(FR)
L’invention concerne un procédé de fabrication d'une tranche ayant une partie encoche comprenant : une étape de polissage bilatéral consistant à polir les deux surfaces principales d'une tranche ; une étape de polissage optique de surface à encoche consistant à effectuer un polissage optique sur une section chanfreinée à encoche de la partie encoche ; une étape de polissage optique de surface périphérique externe consistant à effectuer un polissage optique de surface sur la section chanfreinée périphérique externe de la section périphérique externe de la tranche ; et une étape de polissage final consistant à effectuer un polissage final sur une surface principale de la tranche, l'étape de polissage final étant effectuée après l'étape de polissage optique de surface à encoche, l'étape de polissage bilatéral et l'étape de polissage optique de surface périphérique externe.
(JA)
ノッチ部を有するウェーハの製造方法は、ウェーハの両主面を研磨する両面研磨工程と、ノッチ部のノッチ面取り部を鏡面研磨するノッチ鏡面研磨工程と、ウェーハにおける外周部の外周面取り部を鏡面研磨する外周鏡面研磨工程と、ウェーハの一方の主面を仕上げ研磨する仕上げ研磨工程とを備え、ノッチ鏡面研磨工程と両面研磨工程と外周鏡面研磨工程とを、当該順序で行った後に、仕上げ研磨工程を行う。
Also published as
KR1020217018755
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