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1. WO2020136764 - METHOD FOR MANUFACTURING ELECTRONIC COMPONENT PACKAGE

Publication Number WO/2020/136764
Publication Date 02.07.2020
International Application No. PCT/JP2018/047917
International Filing Date 26.12.2018
IPC
H01L 21/67 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/301 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
301to subdivide a semiconductor body into separate parts, e.g. making partitions
CPC
H01L 21/67
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; ; Apparatus not specifically provided for elsewhere
Applicants
  • 昭和電工マテリアルズ株式会社 SHOWA DENKO MATERIALS CO., LTD. [JP]/[JP]
Inventors
  • 本田 一尊 HONDA Kazutaka
  • 小川 剛 OGAWA Tsuyoshi
  • 松原 望 MATSUBARA Nozomi
Agents
  • 長谷川 芳樹 HASEGAWA Yoshiki
  • 清水 義憲 SHIMIZU Yoshinori
  • 平野 裕之 HIRANO Hiroyuki
Priority Data
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) METHOD FOR MANUFACTURING ELECTRONIC COMPONENT PACKAGE
(FR) PROCÉDÉ DE FABRICATION D'UN BOÎTIER DE COMPOSANT ÉLECTRONIQUE
(JA) 電子部品パッケージの製造方法
Abstract
(EN)
A method for manufacturing an electronic component package, the method comprising: a first step of preparing an expand tape and multiple chips fixed on the expand tape; a second step of expanding the expand tape, thereby widening the intervals between the multiple chips fixed on the expand tape; a third step of keeping the tension of the expanded expand tape; a fourth step of providing a mask, which has multiple openings, on a carrier or on a board and transferring the multiple chips onto the carrier or onto the board through the openings of the mask; and a fifth step of peeling the expand tape away from the multiple chips and removing the mask from the carrier or from the board, wherein the mask in the fourth step has a first surface provided on the carrier or on the board and a second surface on the opposite side, and the multiple openings each have such a tapering shape that tapers from the second surface down to the first surface.
(FR)
L'invention concerne un procédé de fabrication d'un boîtier de composant électronique, le procédé comprenant : une première étape consistant à préparer une bande d'expansion et de multiples puces fixées sur la bande d'extension; une deuxième étape consistant à étendre la bande d'expansion, ce qui permet d'élargir les intervalles entre les multiples puces fixées sur la bande d'expansion; une troisième étape consistant à maintenir la tension de la bande d'expansion étendue; une quatrième étape consistant à fournir un masque, qui a de multiples ouvertures, sur un support ou sur une carte et à transférer les multiples puces sur le support ou sur la carte à travers les ouvertures du masque; et une cinquième étape consistant à décoller la bande d'expansion de la pluralité de puces et à retirer le masque du support ou de la carte, le masque dans la quatrième étape ayant une première surface disposée sur le support ou sur la carte et une seconde surface sur le côté opposé, et les multiples ouvertures ayant chacune une forme effilée qui s'effile de la seconde surface à la première surface.
(JA)
エキスパンドテープと、当該エキスパンドテープ上に固定された複数のチップと、を準備する第1工程と、エキスパンドテープを延伸することにより、エキスパンドテープ上に固定された複数のチップの間隔を広げる第2工程と、延伸されたエキスパンドテープのテンションを保持する第3工程と、キャリア又は基板上に複数の開口部を有するマスクを設け、当該マスクの開口部を通して、複数のチップをキャリア又は基板に転写する第4工程と、複数のチップからエキスパンドテープを剥離するとともに、キャリア又は基板からマスクを外す第5工程を備える、電子部品パッケージの製造方法であって、 マスクは、第4工程においてキャリア又は基板上に設けられる第1面と、その反対側の第2面とを有し、複数の開口部は第2面から第1面に向かって先細りとなるようなテーパー形状を有する、電子部品パッケージの製造方法。
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