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1. WO2020136141 - DEVICE AND METHOD FOR PROTECTING A MEMORY

Publication Number WO/2020/136141
Publication Date 02.07.2020
International Application No. PCT/EP2019/086849
International Filing Date 20.12.2019
IPC
G11C 7/24 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
24Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
G11C 8/20 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
20Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
G06F 12/14 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
14Protection against unauthorised use of memory
G06F 13/16 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
G11C 11/406 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
406Management or control of the refreshing or charge-regeneration cycles
G11C 11/408 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
408Address circuits
CPC
G06F 12/1408
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
14Protection against unauthorised use of memory ; or access to memory
1408by using cryptography
G06F 21/85
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
82Protecting input, output or interconnection devices
85interconnection devices, e.g. bus-connected or in-line devices
G06F 2212/1032
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
10Providing a specific technical effect
1032Reliability improvement, data loss prevention, degraded operation etc
G06F 2212/1052
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
10Providing a specific technical effect
1052Security improvement
G11C 11/406
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
406Management or control of the refreshing or charge-regeneration cycles
G11C 11/408
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
408Address circuits
Applicants
  • SECURE-IC SAS [FR]/[FR]
Inventors
  • LE ROLLAND, Michel
  • GUILLEY, Sylvain
  • FACON, Adrien
Agents
  • HNICH-GASRI, Naïma
Priority Data
18306854.327.12.2018EP
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) DEVICE AND METHOD FOR PROTECTING A MEMORY
(FR) DISPOSITIF ET PROCÉDÉ PERMETTANT DE PROTÉGER UNE MÉMOIRE
Abstract
(EN)
Embodiments of the invention provide a memory device (100) comprising a memory (1) comprising at least one chip (2), each chip (2) comprising one or more banks (10) for storing a plurality of bits, each bank (10) comprising a set of rows (13) and columns (14), each row and column comprising a number of bits, the device further comprising a controller (102) configured to generate access commands to the memory(1), an access command identifying an address corresponding to a given row of the memory (1) and a command operation to be performed on said given row, wherein the device further comprises a protection device. The protection device (3) is configured to transform an address, in response to the receipt of an access command identifying said address, into a transformed address. The protection device (3) uses an address storage data structure (30), such as a histogram, to store the transformed address depending on a frequency of access associated with the address, the address storage data structure being reset in response to a memory protection operation (refresh for example) performed in the memory device. The protection device (3) further comprises an access frequency manager (32) configured to determine whether the access frequency associated with an address maintained in the address storage data structure is greater or equal to a threshold, and if so trigger a memory protection operation in the memory (1) from within the memory.
(FR)
Selon certains modes de réalisation, l'invention concerne un dispositif de mémoire (100) comprenant une mémoire (1) comprenant au moins une puce (2), chaque puce (2) comprenant une ou plusieurs banques (10) pour stocker une pluralité de bits, chaque banque (10) comprenant un ensemble de rangées (13) et de colonnes (14), chaque rangée et chaque colonne comprenant un certain nombre de bits, le dispositif comprenant en outre un contrôleur (102) configuré pour générer des commandes d'accès à la mémoire (1), une commande d'accès identifiant une adresse correspondant à une rangée donnée de la mémoire (1) et une opération de commande à effectuer sur ladite rangée donnée, le dispositif comprenant en outre un dispositif de protection. Le dispositif de protection (3) est configuré pour transformer une adresse, en réponse à la réception d'une commande d'accès identifiant ladite adresse, en une adresse transformée. Le dispositif de protection (3) utilise une structure de données de stockage d'adresse (30), telle qu'un histogramme, pour stocker l'adresse transformée en fonction d'une fréquence d'accès associée à l'adresse, la structure de données de stockage d'adresse étant réinitialisée en réponse à une opération de protection de mémoire (rafraîchissement par exemple) effectuée dans le dispositif de mémoire. Le dispositif de protection (3) comprend en outre un gestionnaire de fréquence d'accès (32) configuré pour déterminer si la fréquence d'accès associée à une adresse conservée dans la structure de données de stockage d'adresse est supérieure ou égale à un seuil, et si tel est le cas, déclencher une opération de protection de mémoire dans la mémoire (1) à partir de l'intérieur de la mémoire.
Also published as
Latest bibliographic data on file with the International Bureau